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HY5PS1G831F 数据表(PDF) 4 Page - Hynix Semiconductor |
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HY5PS1G831F 数据表(HTML) 4 Page - Hynix Semiconductor |
4 / 33 page Rev. 1.2 / Dec 2006 4 1HY5PS1G431(L)F 1HY5PS1G831(L)F 1.1 Device Features & Ordering Information 1.1.1 Key Features • VDD=1.8V • VDDQ=1.8V +/- 0.1V • All inputs and outputs are compatible with SSTL_18 interface • Fully differential clock inputs (CK, /CK) operation • Double data rate interface • Source synchronous-data transaction aligned to bidirectional data strobe (DQS, DQS) • Differential Data Strobe (DQS, DQS) • Data outputs on DQS, DQS edges when read (edged DQ) • Data inputs on DQS centers when write(centered DQ) • On chip DLL align DQ, DQS and DQS transition with CK transition • DM mask write data-in at the both rising and falling edges of the data strobe • All addresses and control inputs except data, data strobes and data masks latched on the rising edges of the clock • Programmable CAS latency 3, 4, 5 and 6 supported • Programmable additive latency 0, 1, 2, 3, 4 and 5 supported • Programmable burst length 4/8 with both nibble sequential and interleave mode • Internal eight bank operations with single pulsed RAS • Auto refresh and self refresh supported • tRAS lockout supported • 8K refresh cycles /64ms • JEDEC standard 68ball FBGA(x4/x8) • Full strength driver option controlled by EMRS • On Die Termination supported • Off Chip Driver Impedance Adjustment supported • Read Data Strobe suupported (x8 only) • Self-Refresh High Temperature Entry Ordering Information Part No. Configuration Package HY5PS1G431(L)F-X* 256Mx4 68Ball HY5PS1G831(L)F-X* 128Mx8 Operating Frequency Grade tCK(ns) CL tRCD tRP Unit -E3 533 3 Clk -E4 544 4 Clk -C4 3.75 4 4 4 Clk -C5 3.75 5 5 5 Clk -Y5 355 5 Clk -Y6 366 6 Clk Note: -X* is the speed bin, refer to the Operation Frequency table for complete Part No. 1. Description |
类似零件编号 - HY5PS1G831F |
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类似说明 - HY5PS1G831F |
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