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HY5PS1G421M 数据表(PDF) 26 Page - Hynix Semiconductor |
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HY5PS1G421M 数据表(HTML) 26 Page - Hynix Semiconductor |
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26 / 79 page  Rev. 0.2 / Oct. 2005 26 1HY5PS12421(L)M HY5PS12821(L)M 2.5 Read and Write Access Modes After a bank has been activated, a read or write cycle can be executed. This is accomplished by setting RAS high, CS and CAS low at the clock’s rising edge. WE must also be defined at this time to determine whether the access cycle is a read operation (WE high) or a write operation (WE low). The DDR2 SDRAM provides a fast column access operation. A single Read or Write Command will initiate a serial read or write operation on successive clock cycles. The boundary of the burst cycle is strictly restricted to specific segments of the page length. For example, the 32Mbit x 4 I/O x 4 Bank chip has a page length of 2048 bits (defined by CA0-CA9, CA11). The page length of 2048 is divided into 512 or 256 uniquely addres- sable boundary segments depending on burst length, 512 for 4 bit burst, 256 for 8 bit burst respectively. A 4- bit or 8 bit burst operation will occur entirely within one of the 512 or 256 groups beginning with the column address supplied to the device during the Read or Write Command (CA0-CA9, CA11). The second, third and fourth access will also occur within this group segment, however, the burst order is a function of the starting address, and the burst sequence. A new burst access must not interrupt the previous 4 bit burst operation in case of BL = 4 setting. However, in case of BL = 8 setting, two cases of interrupt by a new burst access are allowed, one reads interrupted by a read, the other writes interrupted by a write with 4 bit burst boundry respectively. The minimum CAS to CAS delay is defined by tCCD, and is a minimum of 2 clocks for read or write cycles. |
类似零件编号 - HY5PS1G421M |
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类似说明 - HY5PS1G421M |
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