HY5PS1G431CFP Datasheet(数据表) 4 Page

部件型号	HY5PS1G431CFP

说明	1Gb DDR2 SDRAM

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制造商	HYNIX [Hynix Semiconductor]

网页	http://www.skhynix.com/kor/main.do

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4 page

Rev. 0.2 /Dec 2006

HY5PS1G431C(L)FP

HY5PS1G831C(L)FP

HY5PS1G1631C(L)FP

1.1 Device Features & Ordering Information

1.1.1 Key Features

• VDD = 1.8V +/- 0.1V

• VDDQ = 1.8V +/- 0.1V

• All inputs and outputs are compatible with SSTL_18 interface

•8 banks

• Fully differential clock inputs (CK, /CK) operation

• Double data rate interface

• Source synchronous-data transaction aligned to bidirectional data strobe (DQS, DQS)

• Differential Data Strobe (DQS, DQS)

• Data outputs on DQS, DQS edges when read (edged DQ)

• Data inputs on DQS centers when write(centered DQ)

• On chip DLL align DQ, DQS and DQS transition with CK transition

• DM mask write data-in at the both rising and falling edges of the data strobe

• All addresses and control inputs except data, data strobes and data masks latched on the rising

edges of the clock

• Programmable CAS latency 3, 4, 5 and 6 supported

• Programmable additive latency 0, 1, 2, 3, 4 and 5 supported

• Programmable burst length 4/8 with both nibble sequential and interleave mode

• Internal eight bank operations with single pulsed RAS

• Auto refresh and self refresh supported

• tRAS lockout supported

• 8K refresh cycles /64ms

• JEDEC standard 60ball FBGA(x4/x8) , 84ball FBGA(x16)

• Full strength driver option controlled by EMRS

• On Die Termination supported

• Off Chip Driver Impedance Adjustment supported

• Read Data Strobe supported (x8 only)

• Self-Refresh High Temperature Entry

Ordering Information

Part No.

Configuration Package

HY5PS1G431C(L)FP-XX*

256Mx4

60 Ball

HY5PS1G831C(L)FP-XX*

128Mx8

HY5PS1G1631C(L)FP-XX*

64Mx16

84 Ball

Operating Frequency

Grade

tCK(ns)

tRCD

tRP

Unit

533

Clk

3.75

Clk

355

Clk

2.5

Clk

Note:

-XX* is the speed bin, refer to the Operation Frequency table for complete Part No.

1. Description

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