SN74GTLP21395

TWO 1-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE BUS TRANSCEIVERS

WITH SPLIT LVTTL PORT, FEEDBACK PATH, AND SELECTABLE POLARITY

SCES350C – JUNE 2001 – REVISED NOVEMBER 2001

3

POST OFFICE BOX 655303

ORDERING INFORMATION

TA

PACKAGE†

ORDERABLE

PART NUMBER

TOP-SIDE

MARKING

SOIC

DW

Tube

SN74GTLP21395DW

GTLP21395

SOIC – DW

Tape and reel

SN74GTLP21395DWR

GTLP21395

–40

°C to 85°C

TSSOP – PW

Tape and reel

SN74GTLP21395PWR

GU395

TVSOP – DGV

Tape and reel

SN74GTLP21395DGVR

GU395

VFBGA – GQN

Tape and reel

SN74GTLP21395GQNR

GU395

† Package drawings, standard packing quantities, thermal data, symbolization, and PCB design

guidelines are available at www.ti.com/sc/package.

functional description

The output-enable (1OEAB, 1OEBY) and polarity-control (1T/C) inputs control 1A, 1B, and 1Y. 2OEAB, 2OEBY,

and 2T/C control 2A, 2B, and 2Y.

OEAB controls the activity of the B port. When OEAB is low, the B-port output is active. When OEAB is high,

the B-port output is disabled.

A separate LVTTL A input and Y output provide a feedback path for control and diagnostics monitoring. OEBY

controls the Y output. When OEBY is low, the Y output is active. When OEBY is high, the Y output is disabled.

T/C selects polarity of data transmission in both directions. When T/C is high, data transmission is true, and

A data goes to the B bus and B data goes to the Y bus. When T/C is low, data transmission is complementary,

and inverted A data goes to the B bus and inverted B data goes to the Y bus.

Function Tables

OUTPUT CONTROL

INPUTS

OUTPUT

MODE

T/C

OEAB

OEBY

OUTPUT

MODE

X

H

H

Z

Isolation

H

L

H

A data to B bus

True transparent

H

H

L

B data to Y bus

True transparent

H

L

L

A data to B bus, B data to Y bus

True transparent

with feedback path

L

L

H

Inverted A data to B bus

Inverted transparent

L

H

L

Inverted B data to Y bus

Inverted transparent

L

L

L

Inverted A data to B bus,

Inverted B data to Y bus

Inverted transparent

with feedback path

OUTPUT EDGE-RATE CONTROL (ERC)

INPUT

ERC

LOGIC LEVEL

OUTPUT

B-PORT

EDGE RATE

H

Slow

L

Fast