Genesis Microchip
gm5020 / gm5020-H Data Sheet
February 2002
C5020-DAT-01Q
iii
Document history
Document
Description
Date
C5020-DAT-01A
Initial Release
June 2000
C5020-DAT-01B
PWM feature documented
June 2000
C5020-DAT-01C
•
Pin R1 (HDATA1) does not require pull-up (See Table 5).
•
FSADDR7 bootstrap functionality corrected.
•
Figure 59 clarified.
•
Character attribute word mapping corrections in Sections 0 and 0.
•
Figure 1 – second EDID EPROM added to clarify the example.
•
YUV(7:0) incorporate General Purpose Inputs (GPIs). See Section
4.19.1 and Table 4.
•
Section 4.19.1,General Purpose Inputs and Outputs (GPIO’s) added.
•
RealColor ™ Flesh tone Adjustment feature documented.
July 2000
C5020-DAT-01D
•
Revised Preliminary AC Characteristics (5.2)
August 2000
C5020-DAT-01E
•
Revised Section 5.1 Preliminary DC Characteristics (Power Figures)
•
Revised Table 3 (TCLK, XTAL)
•
Revised Section 4.1 Clocking Options
•
Added Sections 4.10.10 Input Dithering / Compression and
4.15.2 Output Dithering
•
Minor clarifications to Sections: 4.2.1; 4.3.4; 4.10.3; 4.19.2 and 4.19.3
and to Figures 1 and 3
August 2000
C5020-DAT-01F
•
Revised Table 3 (TCLK, XTAL)
•
Revised Section 4.1 Clocking Options: add 2.7 K pulldown resistor,
TCLK to ground, to maintain correct duty cycle for oscillator
•
Host Interface Port, HDATA(3:0) pins changed to indicate upper nibble
transferred first followed by lower nibble.
•
Minor clarification to REXT pin description
October 2000
C5020-DAT-01G
•
Changed VDD_3.3 and VDD_2.5 MIN and MAX values from TYP +/-
10% to TYP +/- 5% in Table 17.
•
PWM0 and PWM1 have same functionality 4.19.2.
October 2000
C5020-DAT-01H
•
Cosmetic changes to Table 18 - Maximum Speed of Operation
•
Modified recommended HSYNC input circuit in Figure 6 - Example
Signal Terminations
•
Modified Figure 4 –Clock Generation Options for gm5020
•
Added note “(400mV typical hysteresis)” to all Schmitt trigger inputs in
Section 3 - Pin List.
•
Amended I/O column in Table 6 – Display Port Signals
Jan. 2001
C5020-DAT-01I
•
In section 1.2 - Features and Analog RGB Input Port - changed SXGA to
UXGA. In Analog RGB Input Port, changed frequency to 60Hz. In Ultra-
Reliable DVI Receiver, changed frequency to 165MHz.
•
In section 4.3.4, changed range to “10MHz to 162MHz.”
•
In Table 12 changed input clock to 165MHz.
•
In Table 16, changed
θJC rating to 7.8.
•
In Table 17, made extensive changes to parameters and ratings.
•
In Table 18, included maximum speed of operation (200MHz) for R_CLK
Reference Clock. Changed TMDS clock to 165MHz. Changed ADC
Clock to 162MHz. Changed F_CLK_Frame Store Clock speed to
144MHz.
•
In section 14.16.1.1, changed number of words from 3324 to 3594.
•
In section 6, changed Speed to 162MHz.
•
In section 3, corrected references to certain signals.
Feb. 2001
C5020-DAT-01J
•
In first sentence of section 4.16.1.4, corrected reference to bit setting.
April 2001
C5020-DAT-01K
•
In Table 16, changed Input Voltage (5V tolerant inputs) Max to 5.5V
July 2001
C5020-DAT-01L
•
In Table 17, included more details about supply current specifications.
July 2001
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