MYSON
TECHNOLOGY
MTV112A
(Rev 1.9)
MTV112A Revision 1.9 05/18/2001
10/20
P5OUT
45h (r/w)
P57
P56
P55
P54
P53
P52
P51
P50
PCTR6
46h (w)
X
X
X
X
X
X
CLPsel
HALFHsel
INTFLG 50h (r/w) HPRchg VPRchg HPLchg VPLchg
HFchg
VFchg
FIFOI
MI
INTEN
60h (w)
EHPR
EVPR
EHPL
EVPL
EHF
EVF
EFIFO
EMI
INTFLG
51h(r/w)
X
X
X
X
X
X
X
VSYNC
INTEN
61h(w)
X
X
X
X
X
X
X
EVSI
Present
Check
Digital Filter
Present
Check
Vpre
Frequency
Count
Vfreq
Polarity
Check
Vpol
High
Frequency
Mask
Vself
CVSYNC
Polarity Check &
Sync Seperator
CVpre
Hpol
Hself
Digital Filter
Present Check &
Frequency Count
Hpre
Hfreq
HBpl
VBpl
VBLANK
HBLANK
VSYNC
HSYNC
H/V SYNC Processor Block Diagram
PSTUS (r) :
The status of polarity, presence and static level for HSYNC and VSYNC.
CVpre = 1
→ The extracted CVSYNC is present.
= 0
→ The extracted CVSYNC is not present.
Hpol
= 1
→ HSYNC input is positive polarity.
= 0
→ HSYNC input is negative polarity.
Vpol
= 1
→ VSYNC (CVSYNC) is positive polarity.
= 0
→ VSYNC (CVSYNC) is negative polarity.
Hpre
= 1
→ HSYNC input is present.
= 0
→ HSYNC input is not present.
Vpre
= 1
→ VSYNC input is present.
= 0
→ VSYNC input is not present.
Hoff*
= 1
→ HSYNC input's off-level is high.
= 0
→ HSYNC input's off-level is low.
Voff*
= 1
→ VSYNC input's off-level is high.
= 0
→ VSYNC input's off-level is low.
*Hoff and Voff are valid when Hpre=0 or Vpre=0.
HCNTH (r) :
H-Freq counter's high bits.
Hovf
= 1
→ H-Freq counter overflows; this bit is cleared by H/W when condition removed.
HF10 - HF8 :
3 high bits of H-Freq counter.
HCNTL (r) :
H-Freq counter's low bits.