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TMPR4925 数据表(PDF) 99 Page - Toshiba Semiconductor |
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TMPR4925 数据表(HTML) 99 Page - Toshiba Semiconductor |
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99 / 590 page  Chapter 5 Configuration Register 5-9 5.2.5 Power Down Control Register (PDNCTR) 0xE010 31 30 29 28 27 26 25 16 Reserved PDN Reserved STPCPU Reserved PDNMSK R/W R/W R/W : Type 0 0 0x3FF : Initial value 15 0 PUTCV R/W : Type 0x0000 : Initial value Bits Mnemonic Field Name Description 31 Reserved 30 PDN Power Down Trigger Power Down Trigger (Initial value: 0, R/W) This bit is a trigger for the Power Down Sequence. It is set to 0 upon reset and a 0 to 1 transition will initiate the power down sequence. This bit is not cleared to 0 automatically by wakeup from power down. Please clear to 0 before next power down. 29 Reserved 28 STPCPU Stop CPU Clock Stop CPU Clock (Initial value: 0, R/W) When this bit is set to 1, the CPU clock stops after TX49/H2 core operates WAIT instruction and becomes the HALT mode. It is set to 0 upon reset. It is not cleared to 0 automatically by wakeup from power down mode. Please clear to 0 and set to 1 before next CPU clock stop. 27:26 Reserved 25:16 PDNMSK Power Down Mask Power Down Mask (Initial value: 0x3FF, R/W) Indicates which external interrupt signals wake from power down mode. A bit is allocated to each interrupt source. Set 1 and enables wakeup. 1: Interrupt Enabled 0: Interrupt Disabled PDNMSK[9] = RTC PDNMSK[8] = NMI PDNMSK[7] = INT[7] PDNMSK[6] = INT[6] PDNMSK[5] = INT[5] PDNMSK[4] = INT[4] PDNMSK[3] = INT[3] PDNMSK[2] = INT[2] PDNMSK[1] = INT[1] PDNMSK[0] = INT[0] 15:0 PUTCV Power Up Time Counter Value Power Up Time Counter Value (Initial value: 0x0000, R/W) This field determines the number of input clocks that expire after a wakeup has been initiated from STANDBY mode. The clock signal of this counter is MSTRCLK. Figure 5.2.5 Power Down Control Register (PDNCTR) |
类似零件编号 - TMPR4925 |
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类似说明 - TMPR4925 |
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