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EPCS4SI8N 数据表(PDF) 27 Page - Altera Corporation |
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EPCS4SI8N 数据表(HTML) 27 Page - Altera Corporation |
27 / 32 page Altera Corporation Core Version a.b.c variable 4–27 July 2004 Configuration Handbook, Volume 2 Serial Configuration Devices (EPCS1, EPCS4, EPCS16 & EPCS64) Data Sheet Figure 4–18 shows the timing waveform for FPGA AS configuration scheme using a serial configuration device. Figure 4–18. AS Configuration Timing Table 4–14 shows the timing parameters for AS configuration mode. Read Address bit N − 1 bit N bit 1 bit 0 tH tCL tCH tSU 136 Cycles nSTATUS nCONFIG CONF_DONE nCSO DCLK ASDO DATA0 INIT_DONE User I/O User Mode tPOR Table 4–14. Timing Parameters for AS Configuration Symbol Parameter Min Typ Max Unit fCLK DCLK frequency from Cyclone FPGA 14 17 20 MHz fCLK DCLK frequency from Stratix II or Cyclone II FPGA (1) 20 (2) 26 (2) 40 (2) MHz 10 13 20 MHz tCH DCLK high time 25 ns tCL DCLK low time 25 ns tH Data hold time after rising edge on DCLK 0ns tSU Data set up time before rising edge on DCLK 5ns tPOR POR delay 100 ms Notes to Table 4–14: (1) These values are preliminary (2) Only the EPCS16 and EPCS64 devices support a DCLK frequency up to 40 MHz. |
类似零件编号 - EPCS4SI8N |
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类似说明 - EPCS4SI8N |
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