Altera Corporation

Core Version a.b.c variable

4–7

July 2004

Configuration Handbook, Volume 2

Serial Configuration Devices (EPCS1, EPCS4, EPCS16 & EPCS64) Data Sheet

Figure 4–3. FPGA Configuration in AS Mode (Serial Configuration Device Programmed by APU or Third-Party

Programmer)

Notes to Figures 4–2 and 4–3:

(1)

(2)

Serial configuration devices cannot be cascaded.

(3)

Connect the FPGA

MSEL[] input pins to select the AS configuration mode. For details, refer to the appropriate

FPGA family chapter in the Configuration Handbook.

The FPGA acts as the configuration master in the configuration flow and

provides the clock to the serial configuration device. The FPGA enables

the serial configuration device by pulling the

nCS signal low via the nCSO

signal (See Figures 4–2 and 4–3). Subsequently, the FPGA sends the

instructions and addresses to the serial configuration device via the

ASDO

signal. The serial configuration device responds to the instructions by

sending the configuration data to the FPGA’s

DATA0 pin on the falling

edge of

DCLK. The data is latched into the FPGA on the DCLK signal’s

rising edge.

The FPGA controls the

nSTATUS and CONF_DONE pins during

configuration in AS mode. If the

CONF_DONE signal does not go high at

the end of configuration or if the signal goes high too early, the FPGA will

pulse its

nSTATUS pin low to start reconfiguration. Upon successful

configuration, the FPGA releases the

CONF_DONE pin, allowing the

external 10-k

Ωresistor to pull this signal high. Initialization begins after

the

CONF_DONE goes high. After initialization, the FPGA enters user

mode.

f

For more information on configuring Stratix II FPGAs in AS mode or

other configuration modes, see Configuring Stratix II Devices in the

Configuration Handbook.

DATA

DCLK

nCS

ASDI

DATA0

DCLK

nCSO

nCE

nCONFIG

nSTATUS

MSEL[n]

nCEO

CONF_DONE

ASDO

10 k

Ω

10 k

Ω

10 k

Ω

(3)

n

Stratix II or

Cyclone Series FPGA

Serial

Configuration

Device (2)

N.C.