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MC13281B 数据表(PDF) 7 Page - Motorola, Inc

部件名 MC13281B
功能描述  80/100 MHz Video Processor
Download  12 Pages
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制造商  MOTOROLA [Motorola, Inc]
网页  http://www.freescale.com
标志 MOTOROLA - Motorola, Inc

MC13281B 数据表(HTML) 7 Page - Motorola, Inc

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MC13280AY MC13281A/B
7
MOTOROLA ANALOG IC DEVICE DATA
APPLICATION INFORMATION
PCB Layout
Care should be taken in the PCB layout to minimize the
noise effects. The most sensitive pins are VCC, Video VCC,
V5 and Clamp. It is strongly recommended to make a ground
plane and connect VCC/Video VCC and ground traces, to the
power supply directly. Separate power supply traces should
be used for VCC and Video VCC and decoupling capacitors
should be connected as close as possible to the device.
Multi–layer ceramic and tantalum capacitors are
recommended. V5 is designed as a 5.0 V voltage reference
for contrast, and RGB subcontrast controls, so the same
precautions for VCC should also be applied at this pin. The
Clamp capacitors should be connected to ground close to
IC’s ground pin, or power supply ground. The copper trace of
video signal inputs and outputs should be as short as
possible and separated by ground traces to avoid any RGB
cross–interference. A double sided PCB should be used to
optimize the device’s performance.
RGB Input and Output
The RGB output stages are designed as emitter–followers
to drive the CRT driver circuitry directly. The emitter resistors
used are 330
Ω (typically) and the driving current is 15 mA
maximum for each channel. The loading impedance
connected to the output stages should be greater than 330
and less than 5.0 pF for optimum performance (e.g., rise/fall
time, bandwidth, etc.). Decreasing the resistive load will
reduce the rise/fall time by increasing the driving current, but
the output stage may be damaged due to increasing power
dissipation at the same time. The frequency response is
affected by the loading capacitance. The typical value is 3.0
to 5.0 pF. Figure 3 shows a typical interface with a video
output driver. For high resolution color monitor application, it
is recommended to use coaxial cable or shielded cable for
input signal connections.
Clamp and Blank Input
The clamp input is normally (except for Sync–on–Green)
connected to a positive horizontal sync pulse and has a
threshold level of 3.75 V. It is used as a timing reference for
the dc restoration process, so it cannot be an open circuit. If
Sync–on–Green timing mode is used, the clamping pulse
should be located at the horizontal back porch period instead
of horizontal sync. Otherwise, the black level will be clamped
at the wrong dc level.
The blank input is used as a video mute, or horizontal
blanking control pin, and is normally connected to a blanking
pulse generated from the flyback or MCU. The threshold level
is 1.25 V. The blanking pulse width should be equal to the
flyback retrace period to make sure that the video signal is
blanked properly during retrace. It is necessary to limit the
amplitude and avoid any negative undershoot if the flyback
pulse is used. The blanking input pin cannot accept a
negative voltage. This pin should be grounded if it is not used.


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