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PHD36N03LT Datasheet(数据表) 3 Page - NXP Semiconductors |
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PHD36N03LT Datasheet(HTML) 3 Page - NXP Semiconductors |
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3 page 
PHD_PHP36N03LT_2 © Koninklijke Philips Electronics N.V. 2006. All rights reserved. Product data sheet Rev. 02 — 8 June 2006 3 of 13 Philips Semiconductors PHD/PHP36N03LT N-channel TrenchMOS logic level FET Fig 1. Normalized total power dissipation as a function of mounting base temperature Fig 2. Normalized continuous drain current as a function of mounting base temperature Tmb =25 °C; IDM is single pulse; VGS =10V Fig 3. Safe operating area; continuous and peak drain currents as a function of drain-source voltage 03aa16 0 40 80 120 0 50 100 150 200 Tmb ( °C) Pder (%) 03aa24 0 40 80 120 0 50 100 150 200 Tmb (°C) Ider (%) P der P tot P tot 25 °C () ------------------------ 100 % × = I der I D I D25 °C () -------------------- 100 % × = 001aae811 VDS (V) 1 102 10 102 10 103 ID (A) 1 Limit RDSon = VDS / ID tp = 10 µs 100 µs 1 ms DC |
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