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CRD5381 数据表(PDF) 1 Page - Cirrus Logic |
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CRD5381 数据表(HTML) 1 Page - Cirrus Logic |
1 / 24 page Copyright © Cirrus Logic, Inc. 2005 (All Rights Reserved) http://www.cirrus.com Audio A/D Converter w/ Asynchronous Decimation Filter Reference Design Features Analog Performance Advanced Multi-bit Delta-sigma Architecture 24-bit Conversion 120 dB Dynamic Range -110 dB THD+N Performance insensitivity to Input Clock Jitter Digital Filter Characteristics 125 dB Stop-band Rejection Phase-Matched Outputs System Features Output Sample Rate Determined by Input Word, Left/Right, or Fsync Clock No External Master Clock Required Easily Scalable for Additional Channels Sample Rates from 27 kHz to 192 kHz Four-Channel Time-Division Multiplexed Output Two Independent Stereo, Left-Justified Outputs CS5381 A Quad Speed Slave Mode CS5381 B Quad Speed Slave Mode CS8421 A Master Input Slave Ouput CS8421 B Master Input Slave Output Differential Analog Inputs 1-4 TDM ENABLE TDM/SDOUT B SDOUT A 2 2 2 2 LEFT RIGHT RIGHT LEFT PCM Data Ouput/ Serial Clock Input Header, J4 TDM IN LRCK INPUT SCLK INPUT SDOUT SDOUT SDIN SDIN SDOUT SDOUT MAY ‘05 DS563RD1 CRD5381 |
类似零件编号 - CRD5381 |
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类似说明 - CRD5381 |
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