CDB4265

2

DS657DB1

TABLE OF CONTENTS

1. SYSTEM OVERVIEW ............................................................................................................... 4

1.1 Power ................................................................................................................................. 4

1.2 Grounding and Power Supply Decoupling ......................................................................... 4

1.3 CS4265 Audio CODEC ...................................................................................................... 4

1.4 CS8416 Digital Audio Receiver .......................................................................................... 4

1.5 FPGA ................................................................................................................................. 4

1.6 Canned Oscillator .............................................................................................................. 4

1.7 External Control Headers ...................................................................................................5

1.8 Analog Inputs ..................................................................................................................... 5

1.9 Analog Outputs .................................................................................................................. 5

1.10 Serial Control Port ............................................................................................................ 5

1.11 USB Control Port ............................................................................................................. 5

2. SYSTEM CLOCKS AND DATA ................................................................................................ 6

2.1 Clock Routing ..................................................................................................................... 6

2.2 Data Routing ...................................................................................................................... 6

2.2.1 CS4265 SDIN1 and SDIN2 Source ....................................................................... 6

2.2.2 CS4265 TXSDIN Source ....................................................................................... 6

3. PC SOFTWARE CONTROL ..................................................................................................... 7

3.1 CDB4265 Controls Tab ...................................................................................................... 7

3.2 S/PDIF Rx Controls Tab .................................................................................................... 8

3.3 Register Maps Tab ............................................................................................................. 9

3.4 Pre-Configured Script Files ................................................................................................9

3.4.1 Oscillator Clock - Line In to DAC & SPDIF Out ..................................................... 9

3.4.2 SPDIF Recovered Clock - SPDIF In to DAC - ADC to SPDIF Out ...................... 10

4. FPGA REGISTER QUICK REFERENCE ............................................................................... 11

5. FPGA REGISTER DESCRIPTION ......................................................................................... 12

6. CDB CONNECTORS, JUMPERS, AND SWITCHES ............................................................. 16

7. CDB BLOCK DIAGRAM

..................................................................................................... 18

8. CDB SCHEMATICS ............................................................................................................... 19

9. CDB LAYOUT ........................................................................................................................ 27

10. REVISION HISTORY ............................................................................................................ 30