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CS4237B-JQ 数据表(PDF) 7 Page - Cirrus Logic |
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CS4237B-JQ 数据表(HTML) 7 Page - Cirrus Logic |
7 / 114 page TIMING PARAMETERS (TA = 25 °C; VA, VD1, VDF1-VDF4 = +5V; outputs loaded with 30pF Input Levels: Logic 0 = 0V, Logic 1 = VD1) Parameter Symbol Min Max Units E 2PROM Timing (Note 1) SCL Low to SDA Data Out Valid tAA 03.5 µs Start Condition Hold Time tHD:STA 4.0 - µs Clock Low Period tLSCL 4.7 - µs Clock High Period tHSCL 4.0 - µs Start Condition Setup Time (for a Repeated Start Condition) tSU:STA 4.7 - µs Data In Hold Time tHD:DAT 0- µs Data In Setup Time tSU:DAT 250 - ns SDA and SCL Rise Time (Note 7) tR -1 µs SDA and SCL Fall Time tF - 300 ns Stop Condition Setup Time tSU:STO 4.7 - µs Data Out Hold Time tDH 0- ns Notes 7. Rise time on SDA is determined by the capacitance of the SDA line with all connected gates and the external pullup resistor required. XA0/SCL XD0/SDA (IN) XD0/SDA (OUT) tF tHSCL tLSCL t R t SU:STA t HD:STA t HD:DAT t SU:DAT t SU:STO t AA tDH E 2PROM 2-Wire Interface Timing DS213PP4 CS4237B 7 |
类似零件编号 - CS4237B-JQ |
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类似说明 - CS4237B-JQ |
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