AD73411 datasheet(23/36 Pages) AD

部件名	AD73411

功能描述	Low-Power Analog Front End with DSP Microcomputer

Download	36 Pages

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制造商	AD [Analog Devices]

网页	http://www.analog.com

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23 / 36 page

REV. 0

AD73411

–23–

Terminating Unused Pin

The following chart shows the recommendations for terminating

unused pins.

Pin Terminations

I/O

Hi-Z

*

3-State

Reset

Caused

Unused

Name

(Z)

State

By

Conﬁguration

XTAL

I

Float

CLKOUT

O

Float

A13:1 or

O (Z)

Hi-Z

BR, EBR

Float

IAD12:0

I/O (Z)

Hi-Z

IS

Float

A0

O (Z)

Hi-Z

BR, EBR

Float

D23:8

I/O (Z)

Hi-Z

BR, EBR

Float

D7 or

I/O (Z)

Hi-Z

BR, EBR

Float

IWR

I

High (Inactive)

D6 or

I/O (Z)

Hi-Z

BR, EBR

Float

IRD

II

BR, EBR

High (Inactive)

D5 or

I/O (Z)

Hi-Z

Float

IAL

I

Low (Inactive)

D4 or

I/O (Z)

Hi-Z

BR, EBR

Float

IS

I

High (Inactive)

D3 or

I/O (Z)

Hi-Z

BR, EBR

Float

IACK

Float

D2:0 or

I/O (Z)

Hi-Z

BR, EBR

Float

IAD15:13

I/O (Z)

Hi-Z

IS

Float

PMS

O (Z)

O

BR, EBR

Float

DMS

O (Z)

O

BR, EBR

Float

BMS

O (Z)

O

BR, EBR

Float

IOMS

O (Z)

O

BR, EBR

Float

CMS

O (Z)

O

BR, EBR

Float

RD

O (Z)

O

BR, EBR

Float

WR

O (Z)

O

BR, EBR

Float

BR

I

High (Inactive)

BG

O (Z)

O

EE

Float

BGH

O

Float

IRQ2/PF7

I/O (Z)

I

Input = High (Inactive)

or Program as Output,

Set to 1, Let Float

IRQL1/PF6 I/O (Z)

I

Input = High (Inactive)

or Program as Output,

Set to 1, Let Float

IRQL0/PF5 I/O (Z)

I

Input = High (Inactive)

or Program as Output,

Set to 1, Let Float

IRQE/PF4

I/O (Z)

I

Input = High (Inactive)

or Program as Output,

Set to 1, Let Float

SCLK0

I/O

I

Input = High or Low,

Output = Float

RFS0

I/O

I

High or Low

DR0

I

High or Low

TFS0

I/O

O

High or Low

DT0

O

Float

SCLK1

I/O

I

Input = High or Low,

Output = Float

RFS1/

IRQ0 I/O

I

High or Low

DR1/FI

I

High or Low

TFS1/

IRQ1 I/O

O

High or Low

DT1/FO

O

Float

EE

I

EBR

II

EBG

OO

ERESET

II

EMS

OO

EINT

II

ECLK

I

ELIN

I

ELOUT

O

NOTES

*Hi-Z = High Impedance.

1. If the CLKOUT pin is not used, turn it OFF.

2. If the Interrupt/Programmable Flag pins are not used, there are two options:

Option 1: When these pins are conﬁgured as INPUTS at reset and function

as interrupts and input flag pins, pull the pins High (inactive).

Option 2: Program the unused pins as OUTPUTS, set them to 1, and let

them float.

3. All bidirectional pins have three-stated outputs. When the pins is conﬁgured

as an output, the output is Hi-Z (high impedance) when inactive.

4. CLKIN,

RESET, and PF3:0 are not included in the table because these pins

must be used.

Interrupts

The interrupt controller allows the processor to respond to the

eleven possible interrupts and

RESET with minimum overhead.

The AD73411 provides four dedicated external interrupt

input pins,

IRQ2, IRQL0, IRQL1, and IRQE. In addition,

SPORT1 may be reconﬁgured for

IRQ0, IRQ1, FLAG_IN,

and FLAG_OUT, for a total of six external interrupts. The

AD73411 also supports internal interrupts from the timer, the

byte DMA port, the two serial ports, software, and the power-

down control circuit. The interrupt levels are internally prioritized

and individually maskable (except power-down and reset). The

IRQ2, IRQ0, and IRQ1 input pins can be programmed to be

either level- or edge-sensitive.

IRQL0 and IRQL1 are level-

sensitive and

IRQE is edge-sensitive. The priorities and vector

addresses of all interrupts are shown in Table XVII.

Table XVII. Interrupt Priority and Interrupt Vector Addresses

Interrupt Vector

Source of Interrupt

Address (Hex)

RESET (or Power-Up with PUCR = 1) 0000 (Highest Priority)

Power-Down (Nonmaskable)

002C

IRQ2

0004

IRQL1

0008

IRQL0

000C

SPORT0 Transmit

0010

SPORT0 Receive

0014

IRQE

0018

BDMA Interrupt

001C

SPORT1 Transmit or

IRQ1

0020

SPORT1 Receive or

IRQ0

0024

Timer

0028 (Lowest Priority)

Interrupt routines can either be nested, with higher priority

interrupts taking precedence, or processed sequentially. Interrupts

can be masked or unmasked with the IMASK register. Individual

interrupt requests are logically ANDed with the bits in IMASK;

the highest priority unmasked interrupt is then selected. The

power-down interrupt is nonmaskable.

The AD73411 masks all interrupts for one instruction cycle

following the execution of an instruction that modiﬁes the

IMASK register. This does not affect serial port autobuffering

or DMA transfers.

The interrupt control register, ICNTL, controls interrupt nest-

ing and deﬁnes the

IRQ0, IRQ1, and IRQ2 external interrupts

to be either edge- or level-sensitive. The

IRQE pin is an external

edge-sensitive interrupt and can be forced and cleared. The

IRQL0 and IRQL1 pins are external level-sensitive interrupts.

The IFC register is a write-only register used to force and clear

interrupts. On-chip stacks preserve the processor status and are

automatically maintained during interrupt handling. The stacks

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