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AD8117 数据表(PDF) 6 Page - Analog Devices |
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AD8117 数据表(HTML) 6 Page - Analog Devices |
6 / 32 page AD8117/AD8118 Preliminary Technical Data Rev. PrA | Page 6 of 32 TIMING CHARACTERISTICS (PARALLEL MODE) Limit Parameter Symbol Min Typ Max Unit Parallel Data Setup Time t1 ns WE Pulsewidth t2 ns Parallel Data Hold Time t3 ns WE Pulse Separation t4 ns WE to UPDATE Delay t5 ns UPDATE Pulsewidth t6 ns Propagation Delay, UPDATE to Switch On or Off ns WE, UPDATE Rise and Fall Times ns RESET Time ns Specifications subject to change without notice. t5 t6 t 4 t 2 t1 t3 1 0 1 0 1 = LATCHED WE D0–D5 A0–A4 0 = TRANSPARENT UPDATE Figure 3. Timing Diagram, Parallel Mode Table 3. Logic Levels VIH VIL VOH VOL IIH IIL IOH IOL RESET, SERPAR, WE, D0, D1, D2, D3, D4, D5, A0, A1, A2, A3, A4, UPDATE RESET, SERPAR, WE, D0, D1, D2, D3, D4, D5, A0, A1, A2, A3, A4, UPDATE DATA OUT DATA OUT RESET, SERPAR, WE, D0, D1, D2, D3, D4, D5, A0, A1, A2, A3, A4, UPDATE RESET, SERPAR, WE, D0, D1, D2, D3, D4, D5, A0, A1, A2, A3, A4, UPDATE DATA OUT DATA OUT 2.0 V min 0.8 V max disabled disabled 20 µA max –400 µA max disabled disabled |
类似零件编号 - AD8117 |
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类似说明 - AD8117 |
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