MYSON
TECHNOLOGY
MTV212M32
(Rev 1.1)
Revision 1.1
- 11 -
2000/07/04
6.1 Composite SYNC separation/insertion
The MTV212M32 continuously monitors the input HSYNC, if the vertical SYNC pulse can be extracted from
the input, a CVpre flag is set and user can select the extracted "CVSYNC" for the source of polarity check,
frequency count, and VBLANK output. The CVSYNC will have 8us delay compared to the original signal.
The MTV212M32 can also insert pulse to HBLANK output during composite VSYNC’s active time. The insert
pulse’s width is 1/8 HSYNC period and the insertion frequency can adapt to original HSYNC. The HBLANK
pulse can be disable or enable by setting “NoHins” control bit.
6.2 H/V Frequency Counter
MTV212M32 can discriminate HSYNC/VSYNC frequency and saves the information in XFRs. The 14 bits
Hcounter counts the time of 64xHSYNC period, then load the result into the HCNTH/HCNTL latch. The
output value will be [(128000000/H-Freq) - 1], updated once per VSYNC/CVSYNC period when
VSYNC/CVSYNC is present or continuously updated when VSYNC/CVSYNC is non-present. The 12 bits
Vcounter counts the time between two VSYNC pulses, then load the result into the VCNTH/VCNTL latch.
The output value will be (62500/V-Freq), updated every VSYNC/CVSYNC period. An extra overflow bit
indicates the condition of H/V counter overflow. The VFchg/HFchg interrupt is set when VCNT/HCNT value
changes or overflow. Table 4.2.1 and table 4.2.2 shows the HCNT/VCNT value under the operations of
12MHz.
6.2.1 H-Freq Table
Output Value (14 bits)
H-Freq(KHZ)
12MHz OSC (hex / dec)
1
31.5
0FDEh / 4062
2
37.5
0D54h / 3412
3
43.3
0B8Bh / 2955
4
46.9
0AA8h / 2728
5
53.7
094Fh / 2383
6
60.0
0854h / 2132
7
68.7
0746h / 1862
8
75.0
06AAh / 1706
9
80.0
063Fh / 1599
10
85.9
05D1h / 1489
11
93.8
0554h / 1364
12
106.3
04B3h / 1203
6.2.2 V-Freq Table
Output value (12bits)
V-Freq(Hz)
12MHz OSC (hex / dec)
1
56
45Ch / 1116
2
60
411h / 1041
3
70
37Ch /
892
4
72
364h /
868
5
75
341h /
833
6
85
2DFh /
735
6.3 H/V Present Check
The Hpresent function checks the input HSYNC pulse, Hpre flag is set when HSYNC is over 10KHz or
cleared when HSYNC is under 10Hz. The Vpresent function checks the input VSYNC pulse, the Vpre flag is
set when VSYNC is over 40Hz or cleared when VSYNC is under 10Hz. The HPRchg interrupt is set when
the Hpre value changes. The VPRchg interrupt is set when the Vpre/CVpre value change. However, the
CVpre flag interrupt may be disabled when S/W disable the composite function.
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