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ADSP-21371 数据表(PDF) 1 Page - Analog Devices

部件名 ADSP-21371
功能描述  SHARC Processor
Download  48 Pages
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制造商  AD [Analog Devices]
网页  http://www.analog.com
标志 AD - Analog Devices

ADSP-21371 数据表(HTML) 1 Page - Analog Devices

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Preliminary Technical Data
SHARC and the SHARC logo are registered trademarks of Analog Devices, Inc.
SHARC® Processor
ADSP-21371
Rev. PrA
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective companies.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106 U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.326.8703
©2006 Analog Devices, Inc. All rights reserved.
SUMMARY
High performance 32-bit/40-bit floating point processor
optimized for high performance audio processing
Single-instruction, multiple-data (SIMD) computational
architecture
On-chip memory—1M bit of on-chip SRAM and a dedicated
4M bit of on-chip mask-programmable ROM
Code compatible with all other members of the SHARC family
The ADSP-21371 is available with a 266 MHz core instruction
rate with unique audio centric peripherals such as the digi-
tal applications interface, serial ports, precision clock
generators and more. For complete ordering information,
see Ordering Guide on Page 47
Figure 1. Functional Block Diagram
24
11
32
SDRAM
CO NTRO LLER
3
7
ASYNCHRONOUS
MEMO RY
INTERFACE
ADDRESS
DATA
CONTROL
EXTERNAL PORT
FLAGS4-15
SPI PORT (2)
TIMERS (2)
UART (1)
DIGITAL PERIP HERAL INTE RFACE
GPIO FLAGS/
IRQ/TIMEXP
4
SERIAL PORTS (8)
INPUT DATA POR T/
PDAP
DIGITAL APPLICATIONS INTERFACE
IOD(32)
ADDR
DATA
IO A(24)
4 BLOCKS O F
ON-CHIP MEMORY
1M BI T RAM, 4M BIT ROM
PM DA TA B U S
DM DA TA BU S
32
P M AD DRE SS BUS
DM ADD RES S B US
64
PX REGISTER
PROCESSING
ELEMENT
(PEY)
PROCESSING
ELEMENT
(PEX)
TI MER
INSTRUCTIO N
CACHE
32 X 48-BI T
DAG 1
8X4X32
CORE PRO CESSOR
PROGRAM
SEQUENCER
DMA CONTROLLER
(32 CHANNELS)
S
IOP REGISTER (MEMORY MAPPED)
CONTRO L, STATUS, & DATA BUFFERS
JTAG TEST & EMULATION
DAG2
8X4X32
I/O PROCESSOR
DAI PINS
DPI PINS
64
32
14
20
PRECI SION CLOCK
G ENERAT ORS (4)
TWO WIRE
INTERFACE
32
64
PWM
SPDIF (Rx/Tx)


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