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ADSP-21371 数据表(PDF) 7 Page - Analog Devices |
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ADSP-21371 数据表(HTML) 7 Page - Analog Devices |
7 / 48 page ADSP-21371 Preliminary Technical Data Rev. PrA | Page 7 of 48 | June 2006 SDRAM Controller The SDRAM controller provides an interface to up to four sepa- rate banks of industry-standard SDRAM devices or DIMMs, at speeds up to fSCLK. Fully compliant with the SDRAM standard, each bank can has it's own memory select line (MS0–MS3), and can be configured to contain between 16M bytes and 128M bytes of memory. SDRAM external memory address space is shown in Table 4. The controller maintains all of the banks as a contiguous address space so that the processor sees this as a single address space, even if different size devices are used in the different banks. A set of programmable timing parameters is available to config- ure the SDRAM banks to support slower memory devices. The memory banks can be configured as 16 bits wide. The SDRAM controller address, data, clock, and command pins can drive loads up to 30 pF. For larger memory systems, the SDRAM controller external buffer timing should be selected and external buffering should be provided so that the load on the SDRAM controller pins does not exceed 30 pF. Note that the external memory bank addresses shown are for normal word accesses. If 48-bit instructions are placed in any such bank (with two instructions packed into three 32-bit loca- tions), then care must be taken to map data buffers in the same bank. For example, if 2K instructions are placed starting at the bank 0 base address (0x0020 0000), then the data buffers can be placed starting at an address that is offset by 3K words (0x0020 0C00). Asynchronous Controller The asynchronous memory controller provides a configurable interface for up to four separate banks of memory or I/O devices. Each bank can be independently programmed with dif- ferent timing parameters, enabling connection to a wide variety of memory devices including SRAM, ROM, flash, and EPROM, as well as I/O devices that interface with standard memory con- trol lines. Bank0 occupies a 14.7M word window and banks 1, 2, and 3 occupy a 16M word window in the processor’s address space but, if not fully populated, these windows are not made contiguous by the memory controller logic. The banks can also be configured as 8-bit or 16-bit wide buses for ease of interfac- ing to a range of memories and I/O devices tailored either to high performance or to low cost and power. The asynchronous memory controller is capable of a maximum throughput of 176M bytes/sec using a 44MHz external bus speed. Other features include 8 to 32-bit and 16 to 32-bit pack- ing and unpacking, booting from bank select 1, and support for delay line DMA. ADSP-21371 INPUT/OUTPUT FEATURES The ADSP-21371 I/O processor provides 24 channels of DMA, as well as an extensive set of peripherals. These include a 20 pin digital applications interface which controls: • Eight serial ports • S/PDIF receiver/transmitter • Four precision clock generators • Internal data port/parallel data acquisition port The ADSP-21371 processor also contains a 14 pin digital peripheral interface which controls: • Two general-purpose timers • Two serial peripheral interfaces •One universal asynchronous receiver/transmitter (UART) •An I2C compatible two wire interface DMA Controller The ADSP-21371’s on-chip DMA controller allows data trans- fers without processor intervention. The DMA controller operates independently and invisibly to the processor core, allowing DMA operations to occur while the core is simulta- neously executing its program instructions. DMA transfers can occur between the ADSP-21371’s internal memory and its serial ports, the SPI-compatible (serial peripheral interface) ports, the IDP (input data port), the parallel data acquisition port (PDAP) or the UART. Thirty-two channels of DMA are available on the ADSP-21371—16 via the serial ports, eight via the input data port, two for the UART, two for the SPI interface, two for the external port, and two for memory-to-memory transfers. Pro- grams can be downloaded to the ADSP-21371 using DMA transfers. Other DMA features include interrupt generation upon completion of DMA transfers, and DMA chaining for automatic linked DMA transfers. Delay Line DMA The ADSP-21371 processor provides delay line DMA function- ality. This allows processor reads and writes to external delay line buffers (and hence to external memory) with limited core interaction. Table 3. External Memory for Non SDRAM Addresses Bank Size in words Address Range Bank 0 14M 0x0020 0000 – 0x00FF FFFF Bank 1 16M 0x0400 0000 – 0x04FF FFFF Bank 2 16M 0x0800 0000 – 0x08FF FFFF Bank 3 16M 0x0C00 0000 – 0x0CFF FFFF Table 4. External Memory for SDRAM Addresses Bank Size in words Address Range Bank 0 62M 0x0020 0000 – 0x03FF FFFF Bank 1 64M 0x0400 0000 – 0x07FF FFFF Bank 2 64M 0x0800 0000 – 0x0BFF FFFF Bank 3 64M 0x0C00 0000 – 0x0FFF FFFF |
类似零件编号 - ADSP-21371 |
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类似说明 - ADSP-21371 |
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