ADP1621

Rev. A | Page 7 of 32

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

IN

10

CS

9

PIN

8

GATE

7

PGND

6

ADP1621

TOP VIEW

(Not to Scale)

Figure 4. Pin Configuration

Table 4. Pin Function Descriptions

Pin No.

Mnemonic

Description

1

SDSN

Shutdown and Synchronization Input. Turn the ADP1621 on by driving SDSN high; turn it off by driving SDSN low.

If SDSN is left floating or when the SDSN is pulled low, the ADP1621 goes into shutdown after 50 μs. If synchronization is

needed, synchronize the switching frequency to an external clock by connecting the external clock to the SDSN

pin. An internal 100 kΩ pull-down resistor is connected from SDSN to GND.

2

GND

Ground.

3

COMP

Regulation Control Compensation Node. COMP is the output of the internal transconductance error amplifier.

Connect a series RC from COMP to GND to compensate the regulator. The nominal voltage range for this pin is

1.0 V to 2.0 V.

4

FB

Feedback Input. FB is the input to the internal transconductance error amplifier. Drive FB from the output voltage

through a resistive voltage divider. The ratio of the voltage divider sets the output voltage. The regulation voltage

at FB is nominally 1.215 V.

5

FREQ

Frequency Control Input. Connect a resistor from FREQ to GND to set the free-running switching frequency

between 100 kHz and 1.5 MHz. The nominal voltage of this pin is 1.4 V.

6

PGND

Power Ground Input. PGND is the ground return for the internal gate driver and the negative input of the internal

current-sense amplifier. Connect PGND to GND as close to the ADP1621 as possible.

7

GATE

Gate Driver Output. The maximum gate driver output is equal to the PIN voltage. GATE drives the gate of the

external n-channel power MOSFET. Connect GATE to the gate of the MOSFET.

8

PIN

Power Input. PIN powers the gate driver output. An internal 5.5 V shunt regulator is connected to this pin. Bypass

PIN to PGND with a 0.1 μF or greater capacitor.

9

CS

Current-Sense Input. CS is the positive input of the current-sense amplifier. When GATE is turned on, the voltage at

the CS pin increases linearly from 0 V to a maximum of 116 mV, and the nominal peak slope-compensation output

current is 70 μA. When GATE is off, the CS function is disabled. For current sensing in lossless mode, connect CS to

the drain of the power MOSFET. The absolute maximum voltage at CS is 33 V. For higher accuracy current sensing

or higher switch-node voltages, connect CS to a current-sense power resistor in the source of the power MOSFET.

because load transients can momentarily cause the duty cycle to be greater than 50%, even when the steady-

state duty cycle is less than 50%.

10

IN

Input Voltage. IN powers the ADP1621 internal circuitry. An internal 5.5 V shunt regulator is connected to this pin.

Bypass IN to GND with a 0.1 μF or greater capacitor.