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ADG2128 数据表(PDF) 1 Page - Analog Devices |
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ADG2128 数据表(HTML) 1 Page - Analog Devices |
1 / 28 page I2C® CMOS 8 × 12 Unbuffered Analog Switch Array With Dual/Single Supplies ADG2128 Rev. A Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibilityis assumedbyAnalogDevicesforitsuse,norforanyinfringements of patents or other rightsofthirdpartiesthatmayresultfromitsuse.Specificationssubjecttochangewithoutnotice.No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2006 Analog Devices, Inc. All rights reserved. FEATURES I2C-compatible interface 3.4 MHz high speed I2C option 32-lead LFCSP_VQ (5 mm × 5 mm) Double-buffered input logic Simultaneous update of multiple switches Up to 300 MHz bandwidth Fully specified at dual ±5 V/single +12 V operation On resistance 35 Ω maximum Low quiescent current < 20 μA APPLICATIONS AV switching in TV Automotive infotainment AV receivers CCTV Ultrasound applications KVM switching Telecom applications Test equipment/instrumentation PBX systems GENERAL DESCRIPTION The ADG2128 is an analog cross point switch with an array size of 8 × 12. The switch array is arranged so that there are eight columns by 12 rows, for a total of 96 switch channels. The array is bidirectional, and the rows and columns can be configured as either inputs or outputs. Each of the 96 switches can be addressed and configured through the I2C- compatible interface. Standard, full speed, and high speed (3.4 MHz) I2C interfaces are supported. Any simultaneous switch combination is allowed. An additional feature of the ADG2128 is that switches can be updated simultaneously, using the LDSW command. In addition, a RESET option allows all of the switch channels to be reset/off. At power-on, all switches are in the off condition. The device is packaged in a 32-lead, 5 mm × 5 mm LFCSP_VQ. FUNCTIONAL BLOCK DIAGRAM ADG2128 VDD VSS VL SCL SDA X0 TO X11 (I/O) 8 × 12 SWITCH ARRAY LDSW 96 1 96 1 INPUT REGISTER AND 7 TO 96 DECODER LATCHES LDSW GND A0 A1 A2 Y0 TO Y7 (I/O) Figure 1. |
类似零件编号 - ADG2128 |
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类似说明 - ADG2128 |
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