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ADG791GBCPZ-500RL7 数据表(PDF) 8 Page - Analog Devices

部件名 ADG791GBCPZ-500RL7
功能描述  IC-Compatible, Wide Bandwidth, Quad, 2:1 Multiplexer
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制造商  AD [Analog Devices]
网页  http://www.analog.com
标志 AD - Analog Devices

ADG791GBCPZ-500RL7 数据表(HTML) 8 Page - Analog Devices

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ADG791A/ADG791G
Rev. 0 | Page 8 of 24
Parameter1
Conditions
Min
Max
Unit
Description
t11A
Standard mode
1000
ns
tRCL1, rise time of SCL signal after a repeated start condition
and after an acknowledge bit.
Fast mode
20 + 0.1 CB
B
300
ns
High speed mode
CB = 100 pF max
10
80
ns
CB = 400 pF max
20
160
ns
t12
Standard mode
300
ns
tFCL, fall time of SCL signal
Fast mode
20 + 0.1 CB
B
300
ns
High speed mode
CB = 100 pF max
10
40
ns
CB = 400 pF max
20
80
ns
tSP
Fast mode
0
50
ns
Pulse width of suppressed spike
High speed mode
0
10
ns
1 Guaranteed by initial characterization. CB refers to capacitive load on the bus line, tr and tf measured between 0.3 VDD and 0.7 VDD.
2 A device must provide a data hold time for SDA to bridge the undefined region of the SCL falling edge.
TIMING DIAGRAM
SCL
SDA
PS
S
P
t8
t6
t5
t3
t10
t9
t4
t6
t1
t7
t2
t11
t12
Figure 2. Timing Diagram for 2-Wire Serial Interface


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