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ADCMP608 Datasheet(数据表) 1 Page - Analog Devices

部件型号  ADCMP608
说明  Rail-to-Rail, Fast, Low Power, 2.5 V to 5.5 V, Single-Supply TTL/CMOS Comparators
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制造商  AD [Analog Devices]
网页  http://www.analog.com
标志 AD - Analog Devices

ADCMP608 Datasheet(HTML) 1 Page - Analog Devices

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Rail-to-Rail, Fast, Low Power, 2.5 V to 5.5 V,
Single-Supply TTL/CMOS Comparators
Preliminary Technical Data
ADCMP608/ACMP609
Rev. PrA
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibilityis assumedbyAnalogDevicesforitsuse,norforanyinfringements of patents or other
rightsofthirdpartiesthatmayresultfromitsuse.Specificationssubjecttochangewithoutnotice.No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
©2006 Analog Devices, Inc. All rights reserved.
FUNCTIONAL BLOCK DIAGRAMS
FEATURES
NONINVERTING
INPUT
INVERTING
INPUT
Q OUTPUT
Q OUTPUT
ADCMP609
+
SDN
LE/HYS
ADCMP608
NONINVERTING
INPUT
INVERTING
INPUT
Q OUTPUT
+
SDN
10 mV sensitivity rail to rail at VCC = 2.5 V
Input common-mode voltage from −0.2 V to VCC + 0.2 V
Low glitch CMOS-/TTL-compatible output stage
30 ns propagation delay
1 mW at 2.5 V
Shutdown pin
Single-pin control for programmable hysteresis and latch
Power supply rejection >60 dB
−40C° to +125C° operation
APPLICATIONS
High speed instrumentation
Clock and data signal restoration
Logic level shifting or translation
High speed line receivers
Threshold detection
Peak and zero-crossing detectors
Figure 1.
High speed trigger circuitry
Pulse-width modulators
Current-/voltage-controlled oscillators
GENERAL DESCRIPTION
The ADCMP608 and ADCMP609 are fast comparators
fabricated on Analog Devices’ proprietary XFCB2 process.
These comparators are exceptionally versatile and easy to use.
Features include an input range from VEE − 0.5 V to VCC + 0.5 V,
low noise, TTL-/CMOS-compatible output drivers, and latch
inputs with adjustable hysteresis and/or shutdown inputs.
The TTL-/CMOS-compatible output stage is designed to drive
up to 15 pF with full rated timing specs and to degrade in a
graceful and linear fashion as additional capacitance is added.
The comparator input stage offers robust protection against
large input overdrive, and the outputs do not phase reverse
when the valid input signal range is exceeded. High speed latch
and programmable hysteresis features are also provided in a
unique single-pin control option.
The devices offer 30 ns propagation delays driving a 15 pF load
with 5 mV overdrive on 350/400 μA typical supply current. A
flexible power supply scheme allows the devices to operate with
a single +2.5 V positive supply and a −0.5 V to +3.0 V input
signal range up to a +5.5 V positive supply with a −0.5 V to +6V
input signal range. Split input/output supplies, with no
sequencing restrictions on the ADCMP609, support a wide
input signal range while allowing independent output swing
control.
The ADCMP608 is available in a tiny 6-lead SC70 package with
single-ended output and a shutdown pin.
The ADCMP609, available in an 8-lead MSOP package, features
a shutdown pin, single pin latch, and hysteresis control.
+




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