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DS14C239 Datasheet(数据表) 5 Page - National Semiconductor (TI)

[Old version datasheet] Texas Instruments acquired National semiconductor.
部件型号  DS14C239
说明  Dual Supply TIA/EIA-232 3 x 5 Driver/Receiver
下载  8 Pages
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制造商  NSC [National Semiconductor (TI)]
网页  http://www.national.com
标志 NSC - National Semiconductor (TI)

DS14C239 Datasheet(HTML) 5 Page - National Semiconductor (TI)

  DS14C239 数据表 HTML 1Page - National Semiconductor (TI) DS14C239 数据表 HTML 2Page - National Semiconductor (TI) DS14C239 数据表 HTML 3Page - National Semiconductor (TI) DS14C239 数据表 HTML 4Page - National Semiconductor (TI) DS14C239 数据表 HTML 5Page - National Semiconductor (TI) DS14C239 数据表 HTML 6Page - National Semiconductor (TI) DS14C239 数据表 HTML 7Page - National Semiconductor (TI) DS14C239 数据表 HTML 8Page - National Semiconductor (TI)  
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Parameter Measurement Information (Continued)
TLF11283 – 8
FIGURE 5 Receiver Disable Load Circuit
TLF11283 – 9
FIGURE 6 Receiver TRI-STATE Timing (tPHZ tPZH)
TLF11283 – 10
FIGURE 7 Receiver TRI-STATE Timing (tPLZ tPZL)
Pin Descriptions
VCC (pin 4) Power supply pin for the device a5V
(g10%)
V
a
(pin 5)
Positive supply for TIAEIA-232-E drivers
Specified at 75V minimum and 132V maximum
V
b
(pin 8)
Negative supply for TIAEIA-232-E drivers
Recommended external capacitor C2 e 10 mF (16V) This
supply is not intended to be loaded externally
C1
a
C1
b (pins 6 7)
External capacitor connection pins
Recommended capacitor10 mF (16V)
EN (pin 14)
Controls the Receiver output TRI-STATE Cir-
cuit A High level on this pin will disable the Receiver Out-
put
DIN 1–3 (pins 24 23 16) Driver input pins are TTLCMOS
compatible Inputs of unused drivers may be left open an
internal pull-up resistor (500 kX minimum typically 5 MX)
pulls input to VCC Output will be LOW for open inputs
DOUT 1–3 (pins 19 20 13) Driver output pins conform to
TIAEIA-232-E levels
RIN 1–5 (pins 2 21 18 12 9) Receiver input pins accept
TIAEIA-232-E input voltages (g15V) Receivers feature a
noise filter and guaranteed hysteresis of 100 mV Unused
receiver input pins may be left open Internal input resistor
(5 kX) pulls input LOW providing a failsafe HIGH output
ROUT 1–5 (pins 1 22 17 11 10) Receiver output pins
are TTLCMOS compatible Receiver output HIGH voltage
is specified for both CMOS and TTL load conditions
GND (pin 3)
Ground pin
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