AN1504/D

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4

Metastable Equations

Flip−flop propagation delay as a function of the input

signal is represented in Figure 6.

DATA

INPUT

TIME

Figure 6. Flip−Flop Response Time Plot

Dt

The ordinate is the flip−flop propagation delay time, and

the abscissa is the time that data arrives at the flip−flop input

and/or hold times have been violated; and the device enters

will have no affect on the output, hence the output does not

change and the propagation delay is defined as zero.

For devices with zero or negative set−up times the same

response plot applies, however the abscissa is shifted such

that the value of T0 is no longer the clock transition time.

The same concepts are valid for derivation of metastability

equations for each case: positive, negative or zero set−up

and hold times. To clarify the flip−flop response plot,

Figure 7 illustrates a case in which the propagation delay is

prior to a clock transition and is maintained at this level for

the specified hold time. Figure 8 is an example in which the

concept of a failure window to facilitate the characterization

occurs, and is the range of data input times relative to the

is the maximum allowable propagation delay; delays longer

mathematically as:

TW(TD) + TP

10(Dt) t

(eq. 1)

Where:

Nominal Propagation Delay

Delay After Clock That

Constitutes a Failure

t

Flip−Flop Resolution Time Constant

Dt

CLOCK SIGNAL

TIME

DATA SIGNAL

Figure 7. Proper Set−Up and Hold Times

CLOCK SIGNAL

DATA SIGNAL

TIME

Figure 8. Violation of Set−Up and Hold Times