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Z86L7103ZEM Datasheet(数据表) 5 Page - Zilog, Inc.

部件型号  Z86L7103ZEM
说明  ICEBOX FAMILY IN-CIRCUIT EMULATOR-L71
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制造商  ZILOG [Zilog, Inc.]
网页  http://www.zilog.com
标志 ZILOG - Zilog, Inc.

Z86L7103ZEM Datasheet(HTML) 5 Page - Zilog, Inc.

  Z86L7103ZEM 数据表 HTML 1Page - Zilog, Inc. Z86L7103ZEM 数据表 HTML 2Page - Zilog, Inc. Z86L7103ZEM 数据表 HTML 3Page - Zilog, Inc. Z86L7103ZEM 数据表 HTML 4Page - Zilog, Inc. Z86L7103ZEM 数据表 HTML 5Page - Zilog, Inc. Z86L7103ZEM 数据表 HTML 6Page - Zilog, Inc. Z86L7103ZEM 数据表 HTML 7Page - Zilog, Inc.  
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Zilog
In-Circuit Emulator-L71
CP97LVO2100
5
1
8.
The general-purpose registers after Power-On Reset
or at initial emulator use will be different than the actual
device. The emulator self-test will always leave the
same values in the general-purpose registers, while
the real device will have a random or undefined value.
9.
Power Supply ramp-up/rise time must be such that
when the minimum power-on reset time (Tpor)
expires, the V
CC must be in the supported specified
operating range of the device.
10. If Program Counter jumps to an unknown address:
a.
Stack is not set to internal. Register %F8 (P01M
Register) bit D2 not set to state “1”.
b.
Stack Pointer Register %FE(SPH) and Register
%FF(SPL) are not initialized. For internal Stack,
SPH does not have to be initialized since it is not
used. The SPH and SPL are reset to 00H after any
reset or Stop-Mode Recovery.
c.
Any instruction other than “DI” was used to disable
interrupts.
d.
The Stack overflowed into the general-purpose
register locations.
e.
Extra “POP”, “PUSH”. “IRET”, or “RET” was
encountered.
f.
When making changes to the IMR register, the
GLOBAL interrupts must be disabled first using DI
instruction.
11. If the Program keeps resetting:
a.
Program Counter rolled over from value “FFFF” to
“0000” and proceeded back to beginning of
program.
b.
Watch-Dog Timer (WDT) was not refreshed from
devices with WDT feature.
12. Check the T
POR and TWDT specifications of the device
that you wish to emulate. The actual specification may
differ from the ICE chip specifications. The Z86C50
ICE chip typical WDT time period is configured using
bits 0 and 1 of the WDTMR register located in Bank F
of the Expanded Register Group at address 0FH.
Note: Typical Z86C50 T
POR = 6.0 ms.
13. Do not start the emulator with OTP device in the
programming socket, as the emulator may not start up
correctly.
14. A shorted PLCC or DIP OTP can crash the emulator
when inserted into the OTP programming socket. If a
PLCC part is inserted in such a way as to cause a
temporary short, then functionality is lost. An attempt
to perform BLANK CHECK on such a part will cause
the “hourglass” to appear continuously. The Windows
application must be reset and restarted.
15. The status color bar in OTP dialog box will be cleared
in the area where a new window opens on top of it.
16. Do not press the emulator MASTER RESET when the
ICEBOX is in the OTP dialog for programming. If
MASTER RESET is pressed while the GUI is doing
OTP programming, close the OTP dialog box and
reopen it to reload the information back to the
hardware.
Note: The ICEBOX is really sitting idle, although the
Command Status shows “Processing” after the GUI
reestablishes the communication link when “Retry”
was selected in the “Out of Synchronization with the
emulator” dialog box.
17. When device serialization is enabled in the OTP
dialog, the GUI copies the current serial number to
code memory immediately before performing a
VERIFY operation. If this behavior is undesirable, then
device serialization should be disabled prior to
invoking the VERIFY operation.
18. The bits of non-implemented features (of devices
having a PCON register) must be set to state “1” on the
emulator.
19. When interrupts are enabled, breakpointing after a
Halt instruction, the emulator will break at the first
instruction in the interrupt service routine that is
serviced when an interrupt occurs.
20. Port 0, Port 1, and Port 2 have auto latches
permanently enabled.
21. SCLK/16 Mode of SMR register is not supported.
22. Programming the ROM protect bit on all Z8 OTPs will
disable all use of the LDC, LDCI, LDE, and LDEI
instructions. Thus, ROM protect does not support the
use of a ROM lookup table. The value must be loaded
as “immediate values”.
The Port 3 Mode Register (R247 P3m) bit D1 must be set
as follows:
Typical Z86C50 ICE Chip WDT Time-Out Period
Internal RC (ms) Time-Out
Bit 1
Bit 0
Z86C50
00
4
01
9
10
18
11
75




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