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CY7C4282V Datasheet(数据表) 5 Page - Cypress Semiconductor

部件型号  CY7C4282V
说明  64K/128Kx9 Low Voltage Deep Sync FIFOs w/ Retransmit & Depth Expansion
下载  15 Pages
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制造商  CYPRESS [Cypress Semiconductor]
网页  http://www.cypress.com
标志 CYPRESS - Cypress Semiconductor

CY7C4282V Datasheet(HTML) 5 Page - Cypress Semiconductor

  CY7C4282V 数据表 HTML 1Page - Cypress Semiconductor CY7C4282V 数据表 HTML 2Page - Cypress Semiconductor CY7C4282V 数据表 HTML 3Page - Cypress Semiconductor CY7C4282V 数据表 HTML 4Page - Cypress Semiconductor CY7C4282V 数据表 HTML 5Page - Cypress Semiconductor CY7C4282V 数据表 HTML 6Page - Cypress Semiconductor CY7C4282V 数据表 HTML 7Page - Cypress Semiconductor CY7C4282V 数据表 HTML 8Page - Cypress Semiconductor CY7C4282V 数据表 HTML 9Page - Cypress Semiconductor Next Button
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CY7C4282V
CY7C4292V
5
Switching Characteristics Over the Operating Range
Parameter
Description
7C4282V/92V
-10
7C4282V/92V
-15
7C4282V/92V
-25
Unit
Min.
Max.
Min.
Max.
Min.
Max.
tS
Clock Cycle Frequency
100
66.7
40
MHz
tA
Data Access Time
2
8
2
10
2
15
ns
tCLK
Clock Cycle Time
10
15
25
ns
tCLKH
Clock HIGH Time
4.5
6
10
ns
tCLKL
Clock LOW Time
4.5
6
10
ns
tDS
Data Set-Up Time
3.5
4
6
ns
tDH
Data Hold Time
0
0
1
ns
tENS
Enable Set-Up Time
3.5
4
6
ns
tENH
Enable Hold Time
0
0
1
ns
tRS
Reset Pulse Width[8]
10
15
25
ns
tRSS
Reset Set-Up Time
8
10
15
ns
tRSR
Reset Recovery Time
8
10
15
ns
tRSF
Reset to Flag and Output Time
10
15
25
ns
tPRT
Retransmit Pulse Width
60
60
60
ns
tRTR
Retransmit Recovery Time
90
90
90
ns
tOLZ
Output Enable to Output in Low Z[9]
0
0
0
ns
tOE
Output Enable to Output Valid
3
7
3
10
3
12
ns
tOHZ
Output Enable to Output in High Z[9]
3
7
3
8
3
12
ns
tWFF
Write Clock to Full Flag
8
10
15
ns
tREF
Read Clock to Empty Flag
8
10
15
ns
tPAF
Clock to Programmable Almost-Full Flag
8
10
15
ns
tPAE
Clock to Programmable Almost-Full Flag
8
10
15
ns
tSKEW1
Skew Time between Read Clock and Write Clock
for Empty Flag and Full Flag
5
6
10
ns
tSKEW2
Skew Time between Read Clock and Write Clock
for Almost-Empty Flag and Almost-Full Flag
10
15
18
ns
Notes:
8.
Pulse widths less than minimum values are not allowed.
9.
Values guaranteed by design, not currently tested.




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