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EM78P350NK 数据表(PDF) 27 Page - ELAN Microelectronics Corp |
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EM78P350NK 数据表(HTML) 27 Page - ELAN Microelectronics Corp |
27 / 110 page EM78P350N 8-Bit Microprocessor with OTP ROM Product Specification (V 1.0) 09.14.2006 • 21 (This specification is subject to change without further notice) Bit 5 (ADE5): AD converter enable bit of P65 pin 0 = Disable AIN5, P65 functions as I/O pin 1 = Enable AIN5, to function as analog input pin Bit 4 (ADE4): AD converter enable bit of P64 pin 0 = Disable AIN4, P64 functions as I/O pin 1 = Enable AIN4 to function as analog input pin Bit 3 (ADE3): AD converter enable bit of P63 pin 0 = Disable AIN3, P63 functions as I/O pin 1 = Enable AIN3, to function as analog input pin Bit 2 (ADE2): AD converter enable bit of P62 pin 0 = Disable AIN2, P62 functions as I/O pin 1 = Enable AIN2, to function as analog input pin Bit 1 (ADE1): AD converter enable bit of P61 pin 0 = Disable AIN1, P61 functions as I/O pin 1 = Enable AIN1, to function as analog input pin Bit 0 (ADE0): AD converter enable bit of P60 pin. 0 = Disable AIN0, P60 functions as I/O pin 1 = Enable AIN0, to function as analog input pin NOTE The P60/AIN0 pin priority is as follows: 6.1.29 Bank 2 R9 (ADCON: ADC Control Register) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 VREFS CKR1 CKR0 ADRUN ADPD ADIS2 ADIS1 ADIS0 Bit 7 (VREFS): The input source of the Vref of the ADC 0 = The Vref of the ADC is connected to Vdd (default value), and the P84/VREF pin carries out the function of P84 1 = The Vref of the ADC is connected to P84/VREF NOTE The P84/VREF pin priority is as follows: P60/ADE0 Priority High Low AIN0 P60 P84/VREF Pin Priority High Low VREF P84 |
类似零件编号 - EM78P350NK |
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类似说明 - EM78P350NK |
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