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AM29PDL127H88VKI 数据表(PDF) 11 Page - SPANSION |
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AM29PDL127H88VKI 数据表(HTML) 11 Page - SPANSION |
11 / 68 page June 07, 2005 Am29PDL127H 9 P RE L I M I NARY PIN DESCRIPTION A22–A0 = 23-bit address bus for 128 Mb de- vice. A9 supports 12 V autoselect in- puts. DQ15–DQ0 = 16-bit data inputs/outputs/float CE# = Chip Enable Inputs OE# = Output Enable Input WE# = Write Enable VSS = Device Ground NC = Pin Not Connected Internally RY/BY# = Ready/Busy output and open drain. When RY/BY#= VIH, the device is ready to accept read operations and commands. When RY/BY#= VOL, the device is either executing an em- bedded algorithm or the device is executing a hardware reset opera- tion. WP#/ACC = Write Protect/Acceleration Input. When WP/ACC#= VIL, the highest and lowest two 4K-word sectors are write protected regardless of other sector protection configurations. When WP/ACC#= VIH, these sector are unprotected unless the DYB or PPB is programmed. When WP/ACC#= 12V, program and erase operations are accelerated. VIO = Input/Output Buffer Power Supply (1.65 V to 1.95 V or 2.7 V to 3.6 V) VCC = Chip Power Supply (2.7 V to 3.6 V) RESET# = Hardware Reset Pin LOGIC SYMBOL 23 16 DQ15–DQ0 A22–A0 CE# OE# WE# RESET# RY/BY# WP#/ACC VIO (VCCQ) |
类似零件编号 - AM29PDL127H88VKI |
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类似说明 - AM29PDL127H88VKI |
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