AD7356BRUZ-500RL7 datasheet(5/18 Pages) AD

部件名	AD7356BRUZ-500RL7

功能描述	Differential Input, Dual, 5 MSPS, 12-Bit, SAR ADC

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制造商	AD [Analog Devices]

网页	http://www.analog.com

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5 / 18 page

Preliminary Technical Data

AD7356

Rev. PrC | Page 5 of 18

TIMING SPECIFICATIONS

VDD = 2.5 V, VDRIVE = 2.5 V to 3.3 V, internal reference = 2.048 V, TA = TMAX to TMIN1, unless otherwise noted.

Table 2.

Parameter

Limit at TMIN, TMAX

Unit

Description

fSCLK

50

kHz min

80

MHz max

tCONVERT

t2 +13 × tSCLK

ns max

AD7356, 12 bit resolution, tSCLK = 1/fSCLK

tQUIET

5

ns min

Minimum time between end of serial read and next falling edge of CS

t2

5

ns min

CS to SCLK setup time

t3

TBD

ns max

Delay from CS until DOUTA and DOUTB are three-state disabled

t42

TBD

ns max

Data access time after SCLK falling edge

t5

0.40 tSCLK

ns min

SCLK low pulse width

t6

0.40 tSCLK

ns min

SCLK high pulse width

t7

TBD

ns min

SCLK to data valid hold time

t8

TBD

ns max

CS rising edge to DOUTA, DOUTB, high impedance

t9

TBD

ns min

CS rising edge to falling edge pulse width

t10

TBD

ns min

SCLK falling edge to DOUTA, DOUTB, high impedance

TBD

ns max

SCLK falling edge to DOUTA, DOUTB, high impedance

Latency

No Latency

1 Temperature ranges are as follows: Y Grade: −40°C to +125°C, B Grade: −40°C to +85°C.

2 The time required for the output to cross 0.4 V or 2.4 V.

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