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QL16X24B Datasheet(数据表) 9 Page - List of Unclassifed Manufacturers

部件型号  QL16X24B
说明  pASIC 1 Family Very-High-Speed CMOS FPGA
下载  10 Pages
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制造商  ETC1 [List of Unclassifed Manufacturers]
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标志 ETC1 - List of Unclassifed Manufacturers

QL16X24B Datasheet(HTML) 9 Page - List of Unclassifed Manufacturers

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QL16x24B
4-29
AC CHARACTERISTICS at VCC = 5V, TA = 25°C (K = 1.00)
Logic Cell
Input Cells
Output Cell
Propagation Delays (ns) [4]
Symbol
Parameter
Output Load Capacitance (pF)
30
50
75
100
150
tOUTLH
Output Delay Low to High
2.7
3.4
4.2
5.0
6.7
tOUTHL
Output Delay High to Low
2.8
3.7
4.7
5.6
7.6
tPZH
Output Delay Tri-state to High
4.0
4.9
6.1
7.3
9.7
tPZL
Output Delay Tri-state to Low
3.6
4.2
5.0
5.8
7.3
tPHZ
Output Delay High to Tri-state [8]
2.9
tPLZ
Output Delay Low to Tri-state [8]
3.3
Notes:
[6]
See High Drive Buffer Table for more information.
[7]
Clock buffer fanout refers to the maximum number of flip flops per half column. The number of half
columns used does not affect clock buffer delay.
[8]
The following loads are used for tPXZ:
Propagation Delays (ns)
Symbol
Parameter
Fanout
12
34
8
tPD
Combinatorial Delay [5]
1.7
2.2
2.6
3.2
5.3
tSU
Setup Time [5]
2.1
2.1
2.1
2.1
2.1
tH
Hold Time
0.0
0.0
0.0
0.0
0.0
tCLK
Clock to Q Delay
1.0
1.5
1.9
2.6
4.7
tCWHI
Clock High Time
2.0
2.0
2.0
2.0
2.0
tCWLO
Clock Low Time
2.0
2.0
2.0
2.0
2.0
tSET
Set Delay
1.7
2.2
2.6
3.2
5.3
tRESET
Reset Delay
1.5
1.9
2.2
2.7
4.4
tSW
Set Width
1.9
1.9
1.9
1.9
1.9
tRW
Reset Width
1.8
1.8
1.8
1.8
1.8
Symbol
Parameter
Propagation Delays (ns) [4]
12
34
6
8
tIN
High Drive Input Delay [6]
2.8
2.9
3.0
3.1
4.0
5.3
tINI
High Drive Input, Inverting Delay [6]
3.0
3.1
3.2
3.3
4.1
5.7
tIO
Input Delay (bidirectional pad)
1.4
1.9
2.2
2.9
4.7
6.5
tGCK
Clock Buffer Delay [7]
2.7
2.8
2.9
3.0
3.1
3.3
tGCKHI
Clock Buffer Min High [7]
2.0
2.0
2.0
2.0
2.0
2.0
tGCKLO
Clock Buffer Min Low [7]
2.0
2.0
2.0
2.0
2.0
2.0
4
5 pF
1K
5 pF
1K
tPHZ
tPLZ




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