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EPM7256B 数据表(PDF) 37 Page - Altera Corporation |
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EPM7256B 数据表(HTML) 37 Page - Altera Corporation |
37 / 66 page Altera Corporation 37 MAX 7000B Programmable Logic Device Data Sheet Table 20. EPM7032B Selectable I/O Standard Timing Adder Delays Notes (1) I/O Standard Parameter Speed Grade Unit -3.5 -5.0 -7.5 Min Max Min Max Min Max 3.3 V TTL/CMOS Input to (PIA) 0.0 0.0 0.0 ns Input to global clock and clear 0.0 0.0 0.0 ns Input to fast input register 0.0 0.0 0.0 ns All outputs 0.0 0.0 0.0 ns 2.5 V TTL/CMOS Input to PIA 0.3 0.4 0.6 ns Input to global clock and clear 0.3 0.4 0.6 ns Input to fast input register 0.2 0.3 0.4 ns All outputs 0.2 0.3 0.4 ns 1.8 V TTL/CMOS Input to PIA 0.5 0.8 1.1 ns Input to global clock and clear 0.5 0.8 1.1 ns Input to fast input register 0.4 0.5 0.8 ns All outputs 1.2 1.8 2.6 ns SSTL-2 Class I Input to PIA 1.3 1.9 2.8 ns Input to global clock and clear 1.2 1.8 2.6 ns Input to fast input register 0.9 1.3 1.9 ns All outputs 0.0 0.0 0.0 ns SSTL-2 Class II Input to PIA 1.3 1.9 2.8 ns Input to global clock and clear 1.2 1.8 2.6 ns Input to fast input register 0.9 1.3 1.9 ns All outputs –0.1 –0.1 –0.2 ns SSTL-3 Class I Input to PIA 1.2 1.8 2.6 ns Input to global clock and clear 0.9 1.3 1.9 ns Input to fast input register 0.8 1.1 1.7 ns All outputs 0.0 0.0 0.0 ns SSTL-3 Class II Input to PIA 1.2 1.8 2.6 ns Input to global clock and clear 0.9 1.3 1.9 ns Input to fast input register 0.8 1.1 1.7 ns All outputs 0.0 0.0 0.0 ns GTL+ Input to PIA 1.6 2.3 3.4 ns Input to global clock and clear 1.6 2.3 3.4 ns Input to fast input register 1.5 2.1 3.2 ns All outputs 0.0 0.0 0.0 ns |
类似零件编号 - EPM7256B |
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类似说明 - EPM7256B |
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