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EPM7064B 数据表(PDF) 53 Page - Altera Corporation

部件名 EPM7064B
功能描述  Programmable Logic Device
Download  66 Pages
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制造商  ALTERA [Altera Corporation]
网页  http://www.altera.com
标志 ALTERA - Altera Corporation

EPM7064B 数据表(HTML) 53 Page - Altera Corporation

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Altera Corporation
53
MAX 7000B Programmable Logic Device Data Sheet
Table 32. EPM7512B Selectable I/O Standard Timing Adder Delays (Part 1 of 2)
Note (1)
I/O Standard
Parameter
Speed Grade
Unit
-5
-7
-10
Min
Max
Min
Max
Min
Max
3.3 V TTL/CMOS
Input to PIA
0.0
0.0
0.0
ns
Input to global clock and clear
0.0
0.0
0.0
ns
Input to fast input register
0.0
0.0
0.0
ns
All outputs
0.0
0.0
0.0
ns
2.5 V TTL/CMOS
Input to PIA
0.4
0.5
0.7
ns
Input to global clock and clear
0.3
0.4
0.5
ns
Input to fast input register
0.2
0.3
0.3
ns
All outputs
0.2
0.3
0.3
ns
1.8 V TTL/CMOS
Input to PIA
0.7
1.0
1.3
ns
Input to global clock and clear
0.6
0.8
1.0
ns
Input to fast input register
0.5
0.6
0.8
ns
All outputs
1.3
1.8
2.3
ns
SSTL-2 Class I
Input to PIA
1.5
2.0
2.7
ns
Input to global clock and clear
1.4
1.9
2.5
ns
Input to fast input register
1.1
1.5
2.0
ns
All outputs
0.0
0.0
0.0
ns
SSTL-2 Class II
Input to PIA
1.5
2.0
2.7
ns
Input to global clock and clear
1.4
1.9
2.5
ns
Input to fast input register
1.1
1.5
2.0
ns
All outputs
–0.1
–0.1
–0.2
ns
SSTL-3 Class I
Input to PIA
1.4
1.9
2.5
ns
Input to global clock and clear
1.2
1.6
2.2
ns
Input to fast input register
1.0
1.4
1.8
ns
All outputs
0.0
0.0
0.0
ns
SSTL-3 Class II
Input to PIA
1.4
1.9
2.5
ns
Input to global clock and clear
1.2
1.6
2.2
ns
Input to fast input register
1.0
1.4
1.8
ns
All outputs
0.0
0.0
0.0
ns
GTL+
Input to PIA
1.8
2.5
3.3
ns
Input to global clock and clear
1.9
2.6
3.5
ns
Input to fast input register
1.8
2.5
3.3
ns
All outputs
0.0
0.0
0.0
ns


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