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TPA5052 Datasheet(数据表) 4 Page - Texas Instruments

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部件型号  TPA5052
说明  STEREO DIGITAL AUDIO LIP-SYNC DELAY
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制造商  TI [Texas Instruments]
网页  http://www.ti.com
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TPA5052 Datasheet(HTML) 4 Page - Texas Instruments

 
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DC CHARACTERISTICS
Serial Audio Input Ports
th1
tsu1
tsu2
th2
DATA
BCLK
(Input)
LRCLK
(Input)
TPA5052
SLOS500A – JUNE 2006 – REVISED AUGUST 2006
T
A = 25°C, VDD = 3 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
IDD
Supply current
VDD = 3.3 V, fs = 48 kHz, BCLK = 32 × fs
1.8
3
mA
IOH
High-level output current
DATA_OUT = 2.6 V
5
13
mA
IOL
Low-level output current
DATA_OUT = 0.4 V
5
13
mA
DATA, LRCLK, BCLK, VI = 5.5V, VDD = 3V
20
IIH
High-level input current
µA
DEL[4:0], VI = 3.6V, VDD = 3.6V
5
IIL
Low-level input current
DATA, LRCLK, BCLK, DEL[4:0], VI = 0V, VDD = 3.6V
1
µA
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
fSCLKIN Frequency, BCLK 32 × fs, 48 × fs, 64 × fs
1.024
12.288
MHz
tsu1
Setup time, LRCLK to BCLK rising edge
10
ns
th1
Hold time, LRCLK from BCLK rising edge
10
ns
tsu2
Setup time, DATA to BCLK rising edge
10
ns
th2
Hold time, DATA from BCLK rising edge
10
ns
LRCLK frequency
32
48
192
kHz
BCLK duty cycle
50%
LRCLK duty cycle
50%
BCLK rising edges between LRCLK rising edges
LRCLK duty cycle = 50%
32
64
BCLK edges
Figure 1. Serial Data Interface Timing
4
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