ADT7461AARMZ-REEL datasheet(5/24 Pages) AD

部件名	ADT7461AARMZ-REEL

功能描述	짹1째C Temperature Monitor with Series Resistance Cancellation

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制造商	AD [Analog Devices]

网页	http://www.analog.com

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ADT7461A

Rev. A | Page 5 of 24

SMBUS TIMING SPECIFICATIONS

Table 3.

Parameter1

Limit at TMIN and TMAX

Unit

Description

fSCLK

400

kHz max

tLOW

1.3

μs min

Clock low period, between 10% points

tHIGH

0.6

μs min

Clock high period, between 90% points

tR

300

ns max

Clock/data rise time

tF

300

ns max

Clock/data fall time

tSU; STA

600

ns min

Start condition setup time

tHD; STA2

600

ns min

Start condition hold time

tSU; DAT

T

3

100

ns min

Data setup time

tSU; STO4

600

ns min

Stop condition setup time

tBUF

1.3

μs min

Bus free time between stop and start conditions

1 Guaranteed by design, but not production tested.

2 Time from 10% of SDATA to 90% of SCLK.

3 Time for 10% or 90% of SDATA to 10% of SCLK.

4 Time for 90% of SCLK to 10% of SDATA.

TIMING DIAGRAM

SCLK

SDATA

tR

tF

tLOW

tHD;DAT

tHD;STA

tHIGH

tSU;DAT

STOP START

STOP

START

tSU;STA

tSU;STO

tHD;STA

tBUF

Figure 2. Serial Bus Timing

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