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AD9219 数据表(PDF) 5 Page - Analog Devices |
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AD9219 数据表(HTML) 5 Page - Analog Devices |
5 / 52 page AD9219 Rev. 0 | Page 5 of 52 DIGITAL SPECIFICATIONS AVDD = 1.8 V, DRVDD = 1.8 V, 2 V p-p differential input, 1.0 V internal reference, AIN = −0.5 dBFS, unless otherwise noted. Table 3. AD9219-40 AD9219-65 Parameter1 Temperature Min Typ Max Min Typ Max Unit CLOCK INPUTS (CLK+, CLK−) Logic Compliance CMOS/LVDS/LVPECL CMOS/LVDS/LVPECL Differential Input Voltage2 Full 250 250 mV p-p Input Common-Mode Voltage Full 1.2 1.2 V Input Resistance (Differential) 25°C 20 20 kΩ Input Capacitance 25°C 1.5 1.5 pF LOGIC INPUTS (PDWN, SCLK/DTP) Logic 1 Voltage Full 1.2 3.6 1.2 3.6 V Logic 0 Voltage Full 0 0.3 0.3 V Input Resistance 25°C 30 30 kΩ Input Capacitance 25°C 0.5 0.5 pF LOGIC INPUT (CSB) Logic 1 Voltage Full 1.2 3.6 1.2 3.6 V Logic 0 Voltage Full 0 0.3 0.3 V Input Resistance 25°C 70 70 kΩ Input Capacitance 25°C 0.5 0.5 pF LOGIC INPUT (SDIO/ODM) Logic 1 Voltage Full 1.2 DRVDD + 0.3 1.2 DRVDD + 0.3 V Logic 0 Voltage Full 0 0.3 0 0.3 V Input Resistance 25°C 30 30 kΩ Input Capacitance 25°C 2 2 pF LOGIC OUTPUT (SDIO/ODM) Logic 1 Voltage (IOH = 50 μA) Full 1.79 1.79 V Logic 0 Voltage (IOL = 50 μA) Full 0.05 0.05 V DIGITAL OUTPUTS (D+, D−), (ANSI-644)1 Logic Compliance LVDS LVDS Differential Output Voltage (VOD) Full 247 454 247 454 mV Output Offset Voltage (VOS) Full 1.125 1.375 1.125 1.375 V Output Coding (Default) Offset binary Offset binary DIGITAL OUTPUTS (D+, D−), (Low Power, Reduced Signal Option)1 Logic Compliance LVDS LVDS Differential Output Voltage (VOD) Full 150 250 150 250 mV Output Offset Voltage (VOS) Full 1.10 1.30 1.10 1.30 V Output Coding (Default) Offset binary Offset binary 1 See the AN-835 Application Note, “Understanding High Speed ADC Testing and Evaluation,” for a complete set of definitions and how these tests were completed. 2 This is specified for LVDS and LVPECL only. |
类似零件编号 - AD9219 |
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类似说明 - AD9219 |
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