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CDC9841DWR 数据表(PDF) 7 Page - Texas Instruments |
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CDC9841DWR 数据表(HTML) 7 Page - Texas Instruments |
7 / 9 page CDC9841 PC MOTHERBOARD CLOCK SYNTHESIZER/DRIVER WITH 3-STATE OUTPUTS SCAS458D – DECEMBER 1994 – REVISED APRIL 1996 7 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PARAMETER MEASUREMENT INFORMATION CLOCK DRIVER CIRCUITS LOAD CIRCUIT Duty Cycle VOLTAGE WAVEFORMS tf tc 2.4 V 1.5 V 0.4 V From Output Under Test CL (see Note A) 500 Ω tr NOTES: A. CL includes probe and jig capacitance. B. The outputs are measured one at a time with one transition per measurement. Figure 1. Load Circuit and Voltage Waveforms PCLK-to-PCLK Skew skew 1.5 V 1.5 V VOH GND VOH GND CPU Clock (PCLK) CPU Clock (PCLK) BCLK-to-BCLK Skew skew 1.5 V 1.5 V VOH GND VOH GND PCI Clock (BCLK) PCI Clock (BCLK) offset 1.5 V 1.5 V VOH GND CPU Clock (PCLK) PCI Clock (BCLK) VOH GND offset PCLK-to-BCLK Offset Figure 2. Waveforms for Calculation of tskew and Offset |
类似零件编号 - CDC9841DWR |
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类似说明 - CDC9841DWR |
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