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83C576 Datasheet(数据表) 5 Page - NXP Semiconductors

部件型号  83C576
说明  80C51 8-bit microcontroller family 8K/256 OTP/ROM, 6 channel 10-bit A/D, 4 comparators, failure detect circuitry, watchdog timer
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制造商  PHILIPS [NXP Semiconductors]
网页  http://www.nxp.com
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83C576 Datasheet(HTML) 5 Page - NXP Semiconductors

 
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Philips Semiconductors
Product specification
83C576/87C576
80C51 8-bit microcontroller family
8K/256 OTP/ROM, 6 channel 10-bit A/D, 4 comparators,
failure detect circuitry, watchdog timer
1998 Jun 04
5
PIN DESCRIPTIONS
PIN NUMBER
MNEMONIC
DIP
LCC
QFP
TYPE
NAME AND FUNCTION
VSS
20
22
16
I
Ground: 0V reference.
VCC
40
44
38
I
Power Supply: This is the power supply voltage for normal, idle, and power-down operation.
P0.0-0.7
39-32
43-36
37-30
I/O
Port 0: Port 0 is a bidirectional I/O port. Port 0 is also the multiplexed low-order address and
data bus during accesses to external program and data memory (see Note 5). In this
application, it uses strong internal pull-ups when emitting 1s. Port 0 also receives code bytes
during parallel EPROM programming and outputs code bytes during verification. External
pull-ups are required during program verification. During reset, the port register is loaded
with 1’s. Port 0 has 4 output modes selected on a per bit basis by writing to the P0M1 and
P0M2 Special Function Registers as follows:
P0M1.x
P0M2.x
Mode Description
0
0
Open drain (default). See Note 1.
0
1
Weak pullup. See Note 2.
1
0
High impedance. See Note 3.
1
1
Push-pull. See Note 4.
Port 0 is also the data I/O port for the Universal Peripheral Interface (UPI). When the UPI is
enabled, port 0 must be configured as High-Z by the user. Input/Output through P0 is
controlled by pin CS, WR, RD, and A0. Output is push-pull when enabled.
P1.0-P1.5
3-8
5-9
42-44
1-3
I/O
Port 1: Port 1 is a 6-bit bidirectional I/O port with Schmitt trigger inputs. Port 1 receives the control
signals during program memory verification and parallel EPROM programming. During reset, port
1 is configured as a high impedance analog input port. Digital push-pull outputs are enabled by
writing 1’s to the P1M1 register. The programmer must take care to prevent digital outputs from
switching while an A/D conversion is in progress. Port 1 has 3 output modes selected on a per bit
basis by writing to the P1M1 and P1M2 special function registers as follows:
P1M1.X
P1M2.X
Mode Description
0
0
A/D only. (High impedance)
0
1
Digital input only. High impedance (default).
1
X
Push-pull.
Port 1 pins also serve alternate functions as follows:
3
4
42
I/O
P1.0/ADIN0
4
5
43
I/O
P1.1/ADIN1
5
6
44
I/O
P1.2/ADIN2
6
7
1
I/O
P1.3/ADIN3
7
8
2
I/O
P1.4/ADIN4
8
9
3
I/O
P1.5/ADIN5
P2.0-P2.7
21-28
24-31
18-25
I/O
Port 2: Port 2 is an 8-bit bidirectional I/O port. Port 2 emits the high-order address byte
during accesses to external program and data memory that use 16-bit addresses (MOVX
@DPTR) (see Note 5). In this application, it uses strong internal pull-ups when emitting 1s.
Port 2 receives the high-order address byte during program verification and parallel EPROM
programming. During reset, the port 2 pullups are turned on synchronously, and the port
register is loaded with 1’s. Port 2 has the following output modes which can be selected on a
per bit basis by writing to P2M1 and P2M0:
P2M1.X
P2M2.X
Mode Description
0
0
Open drain. See Note 1.
0
1
Weak pullup (default). See Note 2.
1
0
High impedance. See Note 3.
1
1
Push-pull. See Note 4.
Port 2 pins serve alternate functions as follows:
21
24
18
P2.0
CEX0
PCA module 0 external I/O
CMP0
comparator 0 output
22
25
19
P2.1
CEX1
PCA module 1 external I/O
CMP1
comparator 1 output
23
26
20
P2.2
CEX2
PCA module 2 external I/O
CMP2
comparator 2 output
24
27
21
P2.3
CEX3
PCA module 3 external I/O
CMP3
comparator 3 output
25
28
22
P2.4
T2EX
timer 2 capture input
A0
UPI address input
26
29
23
P2.5
T2
timer 2 external I/O — clock-out (programmable)
CS
UPI chip select input
27
30
24
P2.6
CEX4
PCA module 4 external I/O
PWM0
Pulse width modulator 0 output
28
31
25
P2.7
ECI
PCA count input
PWM1
Pulse width modulator 1 output




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