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TSB41AB21 数据表(PDF) 9 Page - Texas Instruments

部件名 TSB41AB21
功能描述  IEEE 1394a-2000 TWO-PORT CABLE TRANSCEVER/ARBITER
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制造商  TI [Texas Instruments]
网页  http://www.ti.com
标志 TI - Texas Instruments

TSB41AB21 数据表(HTML) 9 Page - Texas Instruments

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TSB41AB2, TSB41AB2I
IEEE 1394a2000 TWOPORT CABLE
TRANSCEIVER/ARBITER
SLLS424G − JUNE 2000 − REVISED DECEMBER 2004
9
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
Terminal Functions (Continued)
TERMINAL
TYPE
I/O
DESCRIPTION
NAME
NO.
TYPE
I/O
DESCRIPTION
R0
R1
40
41
Bias
Current setting resistor terminals. These terminals are connected through an external resistor to
set the internal operating currents and cable driver output currents. A resistance of 6.34 k
Ω ±1.0%
is required to meet the IEEE Std 1394-1995 output voltage limits.
RESET
53
CMOS
I
Logic reset input. Asserting this terminal low resets the internal logic. An internal pullup resistor
to VDD is provided so only an external delay capacitor is required for proper power-up operation
(see power-up reset in the Application Information section). The RESET terminal also
incorporates an internal pulldown which is activated when the PD input is asserted high. This input
is otherwise a standard logic input, and may also be driven by an open-drain type driver.
SE
28
CMOS
I
Test control input. This input is used in manufacturing test of the TSB41AB2. For normal use this
terminal may be tied to GND through a 1-k
Ω pulldown resistor or it may be tied to GND directly.
SM
29
CMOS
I
Test control input. This input is used in manufacturing test of the TSB41AB2. For normal use this
terminal should be tied to GND.
SYSCLK
2
CMOS
O
System clock output. Provides a 49.152-MHz clock signal, synchronized with data transfers, to
the LLC.
TESTM
27
CMOS
I
Test control input. This input is used in manufacturing test of the TSB41AB2. For normal use this
terminal should be tied to VDD through a 1-kΩ resistor.
TPA0+
TPA1+
37
46
Cable
I/O
Twisted-pair cable A differential signal terminals. Board traces from each pair of positive and
negative differential signal terminals should be kept matched and as short as possible to the
TPA0−
TPA1−
36
45
Cable
I/O
negative differential signal terminals should be kept matched and as short as possible to the
external load resistors and to the cable connector. For an unused port, TPA+ and TPA− can be
left open.
TPB0+
TPB1+
35
44
Cable
I/O
Twisted-pair cable B differential signal terminals. Board traces from each pair of positive and
negative differential signal terminals should be kept matched and as short as possible to the
external load resistors and to the cable connector. For each unused port, TPB+ and TPB−
TPB0−
TPB1−
34
43
Cable
I/O
external load resistors and to the cable connector. For each unused port, TPB+ and TPB−
terminals can be tied together and then connected to ground through a 1-k
Ω resistor or the TPB+
and TPB− terminals can be connected to the suggested termination network.
TPBIAS0
TPBIAS1
38
47
Cable
I/O
Twisted-pair bias output. This provides the 1.86-V nominal bias voltage needed for proper
operation of the twisted-pair cable drivers and receivers, and for signaling to the remote nodes
that there is an active cable connection. Each of these terminals, except for an unused port, must
be decoupled with a 1-
µF capacitor to ground. For the unused port, this terminal can be left
unconnected.
XI
XO
59
60
Crystal
Crystal oscillator inputs. These terminals connect to a 24.576-MHz parallel resonant fundamental
mode crystal. The optimum values for the external shunt capacitors are dependent on the
specifications of the crystal used (see crystal selection in the Application Information section).
When an external clock source is used, XI should be the input and XO should be left open, and
the clock must be supplied before the device is taken out of reset.
NOTE: It is strongly recommended that signals tied to VDD use a 1-kΩ resistor (minimum). Tying signals directly to VCC may result in ESD failures.
Signals tied to ground may be tied directly.


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