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74LVC377 数据表(PDF) 5 Page - NXP Semiconductors |
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74LVC377 数据表(HTML) 5 Page - NXP Semiconductors |
5 / 10 page Philips Semiconductors Product specification 74LVC377 Octal D-type flip-flop with data enable; positive-edge trigger 1998 Jul 29 5 AC CHARACTERISTICS GND = 0V; tr = tf = 2.5ns; CL = 50pF; RL = 500Ω; Tamb = –40°C to +85°C. LIMITS SYMBOL PARAMETER WAVEFORM VCC = 3.3V ±0.3V VCC = 2.7V UNIT MIN TYP1 MAX MIN TYP MAX tPHL tPLH Propagation delay CP to Qn 1 6.0 10.2 6.6 11.2 ns tW Clock pulse width HIGH or LOW 1 4 1.0 5 1.6 ns tsu Set-up time E to CP 2 4 2.3 5 2.9 ns th Hold time E to CP 2 0 –2.2 0 –2.8 ns tsu Set-up time Dn to CP 3 2 1.3 3 1.8 ns th Hold time Dn to CP 3 0 –1.2 0 –1.6 ns fmax Maximum clock pulse frequency 1 125 100 MHz NOTE: 1. Unless otherwise stated, all typical values are at VCC = 3.3V and Tamb = 25°C. AC WAVEFORMS VM = 1.5V at VCC w 2.7V. VM = 0.5 VCC at VCC t 2.7V. VOL and VOH are the typical output voltage drop that occur with the output load. VM VM 1/fMAX tw tPHL tPLH CP INPUT Qn OUTPUT SW00078 GND VOH VOL VI Waveform 1. Clock (CP) to output (Qn) propagation delays the clock pulse width and the maximum clock pulse frequency. SY00061 NOTE: The shaded areas indicate when the input is permitted to change for predictable output performance. VM th th VCC E Input GND VM tsu tsu STABLE tsu th VM tW VCC VCC Dn Input CP Input GND GND Waveform 2. Data set-up and hold times from the data input (Dn) and from the enable input (E) to the clock (CP). |
类似零件编号 - 74LVC377 |
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类似说明 - 74LVC377 |
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