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74LVC163PWDH Datasheet(数据表) 4 Page - NXP Semiconductors

部件型号  74LVC163PWDH
说明  Presettable synchronous 4-bit binary counter; synchronous reset
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制造商  PHILIPS [NXP Semiconductors]
网页  http://www.nxp.com
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74LVC163PWDH Datasheet(HTML) 4 Page - NXP Semiconductors

 
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Philips Semiconductors
Product specification
74LVC163
Presettable synchronous 4-bit binary counter;
synchronous reset
1998 May 20
4
FUNCTIONAL DIAGRAM
PARALLEL LOAD
CIRCUITRY
BINARY
COUNTER
34
56
TC 15
14
13
12
11
Q0
Q1
Q2
Q3
1 MR
2CP
7
D0
D1
D2
D3
CEP
CET
10
PE
9
SY00068
STATE DIAGRAM
8
7
6
5
4
12
11
10
9
13
14
15
0
1
2
3
SF00664
FUNCTION TABLE
OPERATING
INPUTS
OUTPUTS
MODES
MR
CP
CEP
CET
PE
Dn
Qn
TC
Reset (clear)
l
X
X
X
X
L
L
Parallel load
h
X
X
l
l
L
L
Parallel load
h
X
X
l
h
H
*
Count
h
h
h
h
X
count
*
Hold
h
X
l
X
h
X
qn
*
(do nothing)
h
X
X
l
h
X
qn
L
NOTES:
*
=
The TC output is High when CET is High and the counter
is at Terminal Count (HHHH)
H
=
High voltage level
h
=
High voltage level one setup time prior to the Low-to-High
clock transition
L
=
Low voltage level
l
=
Low voltage level one setup time prior to the Low-to-High
clock transition
q
=
Lower case letters indicate the state of the referenced
output one setup time prior to the Low-to-High clock
transition
X
=
Don’t care
=
Low-to-High clock transition
TYPICAL TIMING SEQUENCE
CP
PE
TC
MR
INHIBIT
COUNT
CEP
CET
D0
D2
D1
D3
Q0
Q2
Q1
Q3
RESET PRESET
12
13
14
15
0
1
2
SY00069
Typical timing sequence: reset outputs to zero; preset to binary
twelve; count to thirteen, fourteen, fifteen, zero, one, and two;
inhibit




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