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74LV4052PWDH 数据表(PDF) 11 Page - NXP Semiconductors |
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74LV4052PWDH 数据表(HTML) 11 Page - NXP Semiconductors |
11 / 16 page Philips Semiconductors Product specification 74LV4052 Dual 4-channel analog multiplexer/demultiplexer 1998 Jun 23 11 WAVEFORMS NOTES: 1. VM = 1.5 V at 2.7 V ≤ VCC ≤ 3.6 V VM = 0.5 × VCC at 2.7 V > VCC > 3.6 V 2. VOL and VOH are the typical output voltage drop that occur with the output load 3. Vx = VOL + 0.3 V at 2.7 V ≤ VCC ≤ 3.6 V VX = VOL + 0.1 × VCC at 2.7 V >VCC > 3.6 V VY = VOH – 0.3 V at 2.7 V ≤ VCC ≤ 3.6 V VY = VOH – 0.1 × VCC at 2.7 V >VCC > 3.6 V SV01638 V M V M INPUTS OUTPUTS GND V OL V I V OH tPHL tPLH Figure 13. Input (Vis) to output (Vos) propagation delays. SV01640 outputs disabled outputs enabled outputs enabled tPHZ tPZH tPZL tPLZ VX VY VM VM VM INPUTS OUTPUT HIGH-to-OFF OFF-to-HIGH OUTPUT LOW-to-OFF OFF-to-LOW GND VCC VI VOL VOH GND Figure 14. Turn-on and turn-off times for the inputs (Sn, E) to the output (Vos). TEST CIRCUIT VM VM tW NEGATIVE PULSE 10% 10% 90% 90% 0V VM VM tW VI POSITIVE PULSE 90% 90% 10% 10% 0V tTHL (tf) tTLH (tr)tTHL (tf) tTLH (tr) SY01738 PULSE GENERATOR RT Vl D.U.T. VO CL Vcc 1k W Test Circuit for Outputs Open VEE S1 2 VCC DEFINITIONS VCC VI < 2.7V 2.7 - 3.6V VCC 2.7V Test S1 tPLZ/tPZL tPLH/tPHL tPHZ/tPZH 2 VCC Open VEE > 3.6 V VCC RL = Load resistor CL = Load capacitance includes jig and probe capacitance RT = Termination resistance should be equal to ZOUT of pulse generators. VI VIS Pulse VEE VI tr =tf =6ns, when measuring fmax, there is no constraint on tr, tf with 50% duty factor. 1k W 50 pF VEE Figure 15. Load circuitry for switching times. |
类似零件编号 - 74LV4052PWDH |
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类似说明 - 74LV4052PWDH |
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