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74LV393N 数据表(PDF) 2 Page - NXP Semiconductors |
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74LV393N 数据表(HTML) 2 Page - NXP Semiconductors |
2 / 12 page Philips Semiconductors Product specification 74LV393 Dual 4-bit binary ripple counter 2 1998 Jun 10 853–1936 19545 FEATURES • Optimized for Low Voltage applications: 1.0 to 3.6V • Accepts TTL input levels between V CC = 2.7V and VCC = 3.6V • Typical V OLP (output ground bounce) t 0.8V @ VCC = 3.3V, Tamb = 25°C • Typical V OHV (output VOH undershoot) u 2V @ VCC = 3.3V, Tamb = 25°C • Two 4-bit binary counters with individual clocks • Divide-by any binary module up to 28 in one package • Two master resets to clear each 4-bit counter individually • Output capability: standard • I CC category: MSI DESCRIPTION The 74LV393 is a low–voltage Si-gate CMOS device and is pin and function compatible with 74HC/HCT393. The 74LV393 is a dual 4-bit binary ripple counter with separate clocks (1CP, 2CP) and master reset (1MR, 2MR) inputs to each counter. The operation of each half of the ‘‘393’’ is the same as the ‘‘93’’ except no external clock connections are required. The counters are triggered by a HIGH-to-LOW transition of the clock inputs. The counter outputs are internally connected to provide clock inputs to succeeding stages. The outputs of the ripple counter do not change synchronously and should not be used for high-speed address decoding. The master resets are active-HIGH asynchronous inputs to each 4-bit counter identified by the ‘‘1’’ and ‘‘2’’ in the pin description. A HIGH level on the nMR input overrides the clock and sets the outputs LOW. QUICK REFERENCE DATA GND = 0V; Tamb = 25°C; tr = tf v2.5 ns SYMBOL PARAMETER CONDITIONS TYPICAL UNIT tPHL/tPLH Propagation delay nCP to nQ0 nQ to nQn+1 nMR to nQn CL = 15pF VCC = 3.3V 12 4 11 ns fmax Maximum clock frequency 99 MHz CI Input capacitance 3.5 pF CPD Power dissipation capacitance per flip-flop VI = GND to VCC 1 23 pF NOTE: 1. CPD is used to determine the dynamic power dissipation (PD in µW) PD = CPD VCC2 fi )S (CL VCC2 fo) where: fi = input frequency in MHz; CL = output load capacity in pF; fo = output frequency in MHz; VCC = supply voltage in V; S (CL VCC2 fo) = sum of the outputs. ORDERING INFORMATION PACKAGES TEMPERATURE RANGE OUTSIDE NORTH AMERICA NORTH AMERICA PKG. DWG. # 14-Pin Plastic DIL –40 °C to +125°C 74LV393 N 74LV393 N SOT27-1 14-Pin Plastic SO –40 °C to +125°C 74LV393 D 74LV393 D SOT108-1 14-Pin Plastic SSOP Type II –40 °C to +125°C 74LV393 DB 74LV393 DB SOT337-1 14-Pin Plastic TSSOP Type I –40 °C to +125°C 74LV393 PW 74LV393PW DH SOT402-1 PIN CONFIGURATION SV00672 1CP 1MR 1Q0 1Q2 1Q3 GND VCC 2CP 2MR 2Q0 2Q1 2Q2 2Q3 1 2 3 4 5 6 7 14 13 12 11 10 9 8 1Q1 PIN DESCRIPTION PIN NUMBER SYMBOL FUNCTION 1, 13 1CP, 2CP Clock inputs (HIGH-to-LOW, edge-triggered) 2, 12 1MR, 2MR Asynchronous master reset inputs (active HIGH) 3, 4, 5, 6 11, 10, 9, 8 1Q0 to 1Q3 2Q0 to 2Q3 Flip-flop outputs 7 GND Ground (0V) 14 VCC Positive supply voltage |
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类似说明 - 74LV393N |
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