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74HCT73 数据表(PDF) 10 Page - NXP Semiconductors

部件名 74HCT73
功能描述  Dual JK flip-flop with reset; negative-edge trigger
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制造商  PHILIPS [NXP Semiconductors]
网页  http://www.nxp.com
标志 PHILIPS - NXP Semiconductors

74HCT73 数据表(HTML) 10 Page - NXP Semiconductors

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9397 750 13815
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Product data sheet
Rev. 03 — 12 November 2004
10 of 21
Philips Semiconductors
74HC73
Dual JK flip-flop with reset; negative-edge trigger
th
hold time nJ, nK to nCP
see Figure 6
VCC = 2.0 V
3
−8-
ns
VCC = 4.5 V
3
−3-
ns
VCC = 6.0 V
3
−2-
ns
fmax
maximum clock frequency
see Figure 6
VCC = 2.0 V
6.0
23
-
MHz
VCC = 4.5 V
30
70
-
MHz
VCC = 6.0 V
35
83
-
MHz
VCC = 5.0 V; CL = 15 pF
-
77
-
MHz
CPD
power dissipation capacitance per
flip-flop
VI = GND to VCC
[1] -30
-
pF
Tamb = −40 °C to +85 °C
tPHL, tPLH propagation delay nCP to nQ
see Figure 6
VCC = 2.0 V
-
-
200
ns
VCC = 4.5 V
-
-
40
ns
VCC = 6.0 V
-
-
34
ns
propagation delay nCP to nQ
see Figure 6
VCC = 2.0 V
-
-
200
ns
VCC = 4.5 V
-
-
40
ns
VCC = 6.0 V
-
-
34
ns
propagation delay nR to nQ, nQ
see Figure 7
VCC = 2.0 V
-
-
180
ns
VCC = 4.5 V
-
-
36
ns
VCC = 6.0 V
-
-
31
ns
tTHL, tTLH
output transition time
see Figure 6
VCC = 2.0 V
-
-
95
ns
VCC = 4.5 V
-
-
19
ns
VCC = 6.0 V
-
-
16
ns
tW
nCP clock pulse width HIGH or LOW
see Figure 6
VCC = 2.0 V
100
-
-
ns
VCC = 4.5 V
20
-
-
ns
VCC = 6.0 V
17
-
-
ns
nR reset pulse width HIGH or LOW
see Figure 7
VCC = 2.0 V
100
-
-
ns
VCC = 4.5 V
20
-
-
ns
VCC = 6.0 V
17
-
-
ns
trem
removal time nR to nCP
see Figure 7
VCC = 2.0 V
100
-
-
ns
VCC = 4.5 V
20
-
-
ns
VCC = 6.0 V
17
-
-
ns
Table 8:
Dynamic characteristics …continued
GND = 0 V; tr =tf = 6 ns; CL = 50 pF; see Figure 8.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit


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