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SN74ABT7819A-30PN Datasheet(数据表) 3 Page - Texas Instruments

部件型号  SN74ABT7819A-30PN
说明  512 × 18 × 2 CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY
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制造商  TI [Texas Instruments]
网页  http://www.ti.com
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 3 page
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SN74ABT7819A
512
× 18 × 2
CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY
SCBS756 – MAY 2002
3
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
description (continued)
The state of the B0–B17 outputs is controlled by the port-B chip select (CSB) and the port-B write/read select
(W/RB). When both CSB and W/RB are low, the outputs are active. The B0–B17 outputs are in the
high-impedance state when either CSB or W/RB is high. Data is written to FIFOB–A from port B on the
low-to-high transition of the port-B clock (CLKB) when CSB is low, W/RB is high, the port-B write enable (WENB)
is high, and the port-B input-ready (IRB) flag is high. Data is read from FIFOA–B to the B0–B17 outputs on the
low-to-high transition of CLKB when CSB is low, W/RB is low, the port-B read enable (RENB) is high, and the
port-B output-ready (ORB) flag is high.
The setup- and hold-time constraints for the chip selects (CSA, CSB) and write/read selects (W/RA, W/RB)
enable write and read operations on memory and are not related to the high-impedance control of the data
outputs. If a port read enable (RENA or RENB) and write enable (WENA or WENB) are set low during a clock
cycle, the chip select and write/read select can switch at any time during the cycle to change the state of the
data outputs.
The input-ready (IR) and output-ready (OR) flags of a FIFO are two-stage synchronized to the port clocks for
use as reliable control signals. CLKA synchronizes the status of the input-ready flag of FIFOA–B (IRA) and the
output-ready flag of FIFOB–A (ORA). CLKB synchronizes the status of the input-ready flag of FIFOB–A (IRB)
and the output-ready flag of FIFOA–B (ORB). When the IR flag of a port is low, the FIFO receiving input from
the port is full and writes are disabled to its array. When the OR flag of a port is low, the FIFO that outputs data
to the port is empty and reads from its memory are disabled. The first word loaded to an empty memory is sent
to the FIFO output register at the same time its OR flag is asserted (high). When the memory is read empty and
the OR flag is forced low, the last valid data remains on the FIFO outputs until the OR flag is asserted (high)
again. In this way, a high on the OR flag indicates new data is present on the FIFO outputs.
The SN74ABT7819A is characterized for operation from 0
°C to 70°C.
Function Tables
PORT A
SELECT INPUTS
A0 A17
PORT A OPERATION
CLKA
CSA
W/RA
WENA
RENA
A0–A17
PORT-A OPERATION
X
H
X
X
X
High Z
None
L
H
H
X
High Z
Write A0–A17 to FIFOA–B
L
L
X
H
Active
Read FIFOB–A to A0–A17
PORT B
SELECT INPUTS
B0 B17
PORT B OPERATION
CLKB
CSB
W/RB
WENB
RENB
B0–B17
PORT-B OPERATION
X
H
X
X
X
High Z
None
L
H
H
X
High Z
Write B0–B17 to FIFOB–A
L
L
X
H
Active
Read FIFOA–B to B0–B17




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