Rev. 0.3 / Sep. 2004

4

HY57V643220D(L/S)T(P) Series

4Banks x 512K x 32bits Synchronous DRAM

Pin FUNCTION DESCRIPTIONS

Pin

Pin Name

DESCRIPTION

CLK

Clock

The system clock input. All other inputs are registered to the

SDRAM on the rising edge of CLK.

CKE

Clock Enable

Controls internal clock signal and when deactivated, the SDRAM will

be one of the states among power down, suspend or self refresh

CS

Chip Select

Enables or disables all inputs except CLK, CKE and DQM

BA0, BA1

Bank Address

Selects bank to be activated during RAS activity

Selects bank to be read/written during CAS activity

A0 ~ A10

Address

Row Address : RA0 ~ RA10, Column Address : CA0 ~ CA7

Auto-precharge flag : A10

RAS, CAS, WE

Row Address Strobe,

Column Address Strobe,

Write Enable

RAS, CAS and WE define the operation

Refer function truth table for details

DQM0~3

Data Input/Output Mask

Controls output buffers in read mode and masks input data in write

mode

DQ0 ~ DQ31

Data Input/Output

Multiplexed data input / output pin

VDD/VSS

Power Supply/Ground

Power supply for internal circuits and input buffers

VDDQ/VSSQ

Data Output Power/

Ground

Power supply for output buffers

NC

No Connection

No connection