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WV3HG64M72EER665D7SG 数据表(PDF) 7 Page - White Electronic Designs Corporation |
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WV3HG64M72EER665D7SG 数据表(HTML) 7 Page - White Electronic Designs Corporation |
7 / 11 page WV3HG64M72EER-D7 February 2006 Rev. 2 PRELIMINARY 7 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs AC TIMING PARAMETERS 0°C ≤ TCASE < +70°C; VCCQ = + 1.8V ± 0.1V, VCC = +1.8V ± 0.1V Parameter Symbol 806 665 534 403 Unit Min Max Min Max Min Max Min Max Clock cycle time CL=6 tCK(6) TBD TBD TBD TBD ps CL=5 tCK(5) TBD TBD TBD TBD ps CL=4 tCK(4) TBD TBD TBD TBD 3,750 8,000 5,000 8,000 ps CL=3 tCK(3) TBD TBD TBD TBD 5,000 8,000 5,000 8,000 ps CK high-level width tCH TBD TBD TBD TBD 0.45 0.55 0.45 0.55 tCK CK low-level width tCL TBD TBD TBD TBD 0.45 0.55 0.45 0.55 tCK Half clock period tHP TBD TBD TBD TBD MIN (tCH, tCL) MIN (tCH, tCL) ps Clock jitter tJIT TBD TBD TBD TBD TBD TBD ps DQ output access time from CK/CK# tAC TBD TBD TBD TBD -500 +500 -600 +600 ps Data-out high impedance window from CK/CK# tHZ TBD TBD TBD TBD tAC(MAX) tAC(MAX) ps Data-out low-impedance window from CK/CK# tLZ TBD TBD TBD TBD tAC(MN) tAC(MAX) tAC(MN) tAC(MAX) ps DQ and DM input setup time relative to DQS tDS TBD TBD TBD TBD 100 150 DQ and DM input hold time relative to DQS tQH TBD TBD TBD TBD 225 275 DQ and DM input pulse width (for each input) tDIPW TBD TBD TBD TBD 0.35 0.35 tCK Data hold skew factor tQHS TBD TBD TBD TBD 400 450 ps DQ-DQS hold, DQS to first DQ to go nonvalid, per access tHQ TBD TBD TBD TBD tHP - tQHS tHP - tQHS ps Data valid output window (DVW) tDVW TBD TBD TBD TBD tQH - tDQSQ tQH - tDQSQ ns DQS input high pulse width tDQSH TBD TBD TBD TBD 0.35 0.35 tCK DQS input low pulse width tDQSL TBD TBD TBD TBD 0.35 0.35 tCK DQS output access time from CK/CK# tDQSCK TBD TBD TBD TBD -450 +450 -500 +500 Ps DQS falling edge to CK rising - setup time tDSS TBD TBD TBD TBD 0.2 0.2 tCK DQS falling edge from CK rising - hold time tDSH TBD TBD TBD TBD 0.2 0.2 tCK O DQS-DQ skew, DOS to last DQ valid, per group, per access tDQSQ TBD TBD TBD TBD 300 350 ps DQS read preamble tRPRE TBD TBD TBD TBD 0.9 1.1 0.9 1.1 tCK DQS read postamble tRPST TBD TBD TBD TBD 0.4 0.6 0.4 0.6 tCK DQS write preamble setup time tWPRES TBD TBD TBD TBD 00 ps DQS write preamble tWPRE TBD TBD TBD TBD 0.35 0.35 tCK DQS write postamble tWPST TBD TBD TBD TBD 0.4 0.6 0.4 0.6 tCK Write command to first DQS latching transition tDQSS TBD TBD TBD TBD WL-0.25 WL+0.25 WL-0.25 WL+0.25 tCK AC specification is based on SAMSUNG components. Other DRAM manufacturers specification may be different. Continued on next page |
类似零件编号 - WV3HG64M72EER665D7SG |
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类似说明 - WV3HG64M72EER665D7SG |
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