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WV3HG64M72AER-AD6 Datasheet(数据表) 5 Page - White Electronic Designs Corporation

部件型号  WV3HG64M72AER-AD6
说明  512MB - 64Mx72 DDR2 SDRAM REGISTERED, w/PLL
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制造商  WEDC [White Electronic Designs Corporation]
网页  http://www.whiteedc.com
标志 WEDC - White Electronic Designs Corporation

WV3HG64M72AER-AD6 Datasheet(HTML) 5 Page - White Electronic Designs Corporation

  WV3HG64M72AER-AD6 数据表 HTML 1Page - White Electronic Designs Corporation WV3HG64M72AER-AD6 数据表 HTML 2Page - White Electronic Designs Corporation WV3HG64M72AER-AD6 数据表 HTML 3Page - White Electronic Designs Corporation WV3HG64M72AER-AD6 数据表 HTML 4Page - White Electronic Designs Corporation WV3HG64M72AER-AD6 数据表 HTML 5Page - White Electronic Designs Corporation WV3HG64M72AER-AD6 数据表 HTML 6Page - White Electronic Designs Corporation WV3HG64M72AER-AD6 数据表 HTML 7Page - White Electronic Designs Corporation WV3HG64M72AER-AD6 数据表 HTML 8Page - White Electronic Designs Corporation WV3HG64M72AER-AD6 数据表 HTML 9Page - White Electronic Designs Corporation Next Button
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WV3HG64M72AER-AD6
March 2005
Rev. 1
ADVANCED
5
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
White Electronic Designs
DDR2 IDD SPECIFICATIONS AND CONDITIONS
Includes DDR2 SDRAM components only
Symbol
Proposed Conditions
534
403
Units
IDD0
Operating one bank active-precharge current;
tCK = tCK(IDD), tRC = tRC(IDD), tRAS = tRASmin(IDD); CKE is HIGH, CS\ is HIGH between valid commands;
Address bus inputs are SWITCHING; Data bus inputs are SWITCHING
2,420
2,250
mA
IDD1
Operating one bank active-read-precharge current;
IOUT = 0mA; BL = 4, CL = CL(IDD), AL = 0; tCK = tCK(IDD), tRC = tRC (IDD), tRAS = tRASmin(IDD), tRCD = tRCD(IDD);
CKE is HIGH, CS\ is HIGH between valid commands; Address businputs are SWITCHING; Data pattern is
same as IDAD6W
2,640
2,400
mA
IDD2P
Precharge power-down current;
All banks idle; tCK = tCK(IDD); CKE is LOW; Other control and address bus inputs are STABLE; Data bus
inputs are FLOATING
730
670
mA
IDD2Q
Precharge quiet standby current;
All banks idle; tCK = tCK(IDD); CKE is HIGH, CS\ is HIGH; Other control and address bus inputsare STABLE;
Data bus inputs are FLOATING
1,110
1,040
mA
IDD2N
Precharge standby current;
All banks idle; tCK = tCK(IDD); CKE is HIGH, CS\ is HIGH; Other control and address bus inputs are
SWITCHING; Data bus inputs are SWITCHING
1,090
1,060
mA
IDD3P
Active power-down current;
All banks open; tCK = tCK(IDD); CKE is LOW; Other control and address
bus inputs are STABLE; Data bus inputs are FLOATING
Fast PDN Exit MRS(12) = 0mA
1,190
1,130
mA
Slow PDN Exit MRS(12) = 1mA
600
570
mA
IDD3N
Active standby current;
All banks open; tCK = tCK(IDD), tRAS = tRASmax(IDD), tRP = tRP(IDD); CKE is HIGH, CS\ is HIGH between valid
commands; Other control and address bus inputs are SWITCHING; Data bus inputs are SWITCHING
1,840
1,730
mA
IDAD6W
Operating burst write current;
All banks open, Continuous burst writes; BL = 4, CL = CL(IDD), AL = 0; tCK = tCK(IDD), tRAS = tRASmax(IDD), tRP
= tRP(IDD); CKE is HIGH, CS\ is HIGH between valid commands; Address bus inputs are SWITCHING; Data
bus inputs are SWITCHING
3,550
2,810
mA
IDAD6R
Operating burst read current;
All banks open, Continuous burst reads, IOUT = 0mA; BL = 4, CL = CL(IDD), AL = 0; tCK = tCK(IDD), tRAS =
tRASmax(IDD), tRP = tRP(IDD); CKE is HIGH, CS\ is HIGH between valid commands; Address bus inputs are
SWITCHING; Data pattern is same as IDAD6W
3,230
2,730
mA
IDD5B
Burst auto refresh current;
tCK = tCK(IDD); Refresh command at every tRFC(IDD) interval; CKE is HIGH, CS\ is HIGH between valid
commands; Other control and address bus inputs are SWITCHING; Data bus inputs are SWITCHING
3,610
3,430
mA
IDD6
Self refresh current;
CK and CK\ at 0V; CKE 0.2V; Other control and address bus inputs
are FLOATING; Data bus inputs are FLOATING
740
680
mA
IDD7
Operating bank interleave read current;
All bank interleaving reads, IOUT = 0mA; BL = 4, CL = CL(IDD), AL = tRCD(IDD)-1*tCK(IDD); tCK = tCK(IDD), tRC =
tRC(IDD), tRRD = tRRD(IDD), tRCD = 1*tCK(IDD); CKE is HIGH, CS\ is HIGH between valid commands; Address
bus inputs are STABLE during DESELECTs; Data pattern is same as IDAD6R; Refer to the following page for
detailed timing conditions
5,540
5,210
mA




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