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WV3HG64M72AER-AD6 Datasheet(数据表) 4 Page - White Electronic Designs Corporation

部件型号  WV3HG64M72AER-AD6
说明  512MB - 64Mx72 DDR2 SDRAM REGISTERED, w/PLL
下载  10 Pages
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制造商  WEDC [White Electronic Designs Corporation]
网页  http://www.whiteedc.com
标志 WEDC - White Electronic Designs Corporation

WV3HG64M72AER-AD6 Datasheet(HTML) 4 Page - White Electronic Designs Corporation

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WV3HG64M72AER-AD6
March 2005
Rev. 1
ADVANCED
4
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
White Electronic Designs
RECOMMENDED DC OPERATING CONDITIONS
All Voltages Referenced to VSS
Parameter
Symbol
Rating
Units
Notes
Min.
Type
Max.
Supply Voltage
VCC
1.7
1.8
1.9
V
Supply Voltage for DLL
VCCL
1.7
1.8
1.9
V
4
Supply Voltage for Output
VCCQ
1.7
1.8
1.9
V
4
Input Reference Voltage
VREF
0.49*VCCQ
0.50*VCCQ
0.51*VCCQ
V
1, 2
Termination Voltage
VTT
VREF-0.04
VREF
VREF+0.04
V
3
There is no specific device VCC supply voltage requirement for SSTL-1.8 compliance. However under all conditions VCCQ must be less than or equal to VCC.
1. The value of VREF may be selected by the user to provide optimum noise margin in the system. Typically the value of VREF isexpected to be about 0.5 x VCCQ of the transmitting
device and VREF is expected to track variations in VCCQ.
2. Peak to peak AC noise on VREF may not exceed ±2% VREF(DC).
3. VTT of transmitting device must track VREF of receiving device.
4. AC parameters are measured with VCC, VCCQ and VCCDL tied together.
ABSOLUTE MAXIMUM RATINGS
SSTL_1.8V
Symbol
Parameter
Rating
Units
Notes
VCC
Voltage on VCC pin relative to VSS
- 1.0 V - 2.3 V
V
5
VCCQ
Voltage on VCCQ pin relative to VSS
- 0.5 V - 2.3 V
V
5
VCCL
Voltage on VCCL pin relative to VSS
- 0.5 V - 2.3 V
V
5
VIN, VOUT
Voltage on any pin relative to VSS
- 0.5 V - 2.3 V
V
5
TSTG
Storage Temperature
-55 to +100
C
5, 6
5. Stresses greater than those listed under ìAbsolute Maximum Ratingsî may cause permanent damage to the device. This is a stress rating only and functional operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect reliability.
6. Storage Temperature is the case surface temperature on the center/top side of the DRAM. For the measurement conditions, please refer to JESD51-2 standard.
CAPACITANCE
TA = 25°C, f = 1MHz, VCC = VCCQ = 1.8V
Parameter
Symbol
Max
Units
Input Capacitance: CK, CK#
CCK
11
pF
Input Capacitance: CKE, CS#
CI1
12
pF
Input Capacitance: Addr. RAS#, CAS#, WE#
CI2
12
pF
Input/Output Capacitance: DQ, DQS, DM, DQS#
CIO
10
pF




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