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WV3HG64M64EEU-D6 Datasheet(数据表) 6 Page - White Electronic Designs Corporation

部件型号  WV3HG64M64EEU-D6
说明  512MB - 64Mx64 DDR2 SDRAM UNBUFFERED
下载  11 Pages
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制造商  WEDC [White Electronic Designs Corporation]
网页  http://www.whiteedc.com
标志 WEDC - White Electronic Designs Corporation

WV3HG64M64EEU-D6 Datasheet(HTML) 6 Page - White Electronic Designs Corporation

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WV3HG64M64EEU-D6
December 2005
Rev. 0
ADVANCED
6
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
White Electronic Designs
DDR2 ICC SPECIFICATIONS AND CONDITIONS
Symbol
Proposed Conditions
806
665
534
403
Units
ICC0*
Operating one bank active-precharge current;
tCK = tCK(ICC), tRC = tRC(ICC), tRAS = tRASmin(ICC); CKE is HIGH, CS# is HIGH between valid
commands; Address bus inputs are SWITCHING; Data bus inputs are SWITCHING
TBD
TBD
800
760
mA
ICC1*
Operating one bank active-read-precharge current;
IOUT = 0mA; BL = 4, CL = CL(ICC), AL = 0; tCK = tCK(ICC), tRC = tRC (ICC), tRAS = tRAS MIN(ICC),
tRCD = tRCD(ICC); CKE is HIGH, CS# is HIGH between valid commands; Address bus inputs
are SWITCHING; Data pattern is same as ICC4W
TBD
TBD
880
800
mA
ICC2P**
Precharge power-down current;
All banks idle; tCK = tCK(ICC); CKE is LOW; Other control and address bus inputs are STABLE;
Data bus inputs are FLOATING
TBD
TBD
64
64
mA
ICC2Q**
Precharge quiet standby current;
All banks idle; tCK = tCK(ICC); CKE is HIGH, CS# is HIGH; Other control and address bus
inputs are STABLE; Data bus inputs are FLOATING
TBD
TBD
200
200
mA
ICC2N**
Precharge standby current;
All banks idle; tCK = tCK(ICC); CKE is HIGH, CS# is HIGH; Other control and address bus
inputs are SWITCHING; Data bus inputs are SWITCHING
TBD
TBD
240
240
mA
ICC3P**
Active power-down current;
All banks open; tCK = tCK(ICC); CKE is LOW; Other control
and address bus inputs are STABLE; Data bus inputs are
FLOATING
Fast PDN Exit MRS(12) = 0
TBD
TBD
240
240
mA
Slow PDN Exit MRS(12) = 1
TBD
TBD
120
120
mA
ICC3N**
Active standby current;
All banks open; tCK = tCK(ICC), tRC = tRC(ICC), tRAS = tRAS MIN(ICC); CKE is HIGH, CS# is HIGH
between valid commands; Other control and address bus inputs are SWITCHING; Data bus
inputs are SWITCHING
TBD
TBD
560
520
mA
ICC4W**
Operating burst write current;
All banks open, Continuous burst writes; BL = 4, CL = CL(ICC), AL = 0; tCK = tCK(ICC), tRAS =
tRAS MAX(ICC), tRP = tRP(ICC); CKE is HIGH, CS# is HIGH between valid commands; Address
bus inputs are SWITCHING; Data bus inputs are SWITCHING
TBD
TBD
1600
1160
mA
ICC4R*
Operating burst read current;
All banks open, Continuous burst reads, IOUT = 0mA; BL = 4, CL = CL(ICC), AL = 0; tCK
= tCK(ICC), tRAS = tRAS MAX(ICC), tRP = tRP(ICC); CKE is HIGH, CS# is HIGH between valid
commands; Address bus inputs are SWITCHING; Data pattern is same as ICC4W
TBD
TBD
1440
1160
mA
ICC5B**
Burst auto refresh current;
tCK = tCK(ICC); Refresh command at every tRFC(ICC) interval; CKE is HIGH, CS# is HIGH
between valid commands; Other control and address bus inputs are SWITCHING; Data bus
inputs are SWITCHING
TBD
TBD
1560
1480
mA
ICC6*
Self refresh current;
CK and CK# at 0V; CKE 0.2V; Other control and
address bus inputs are FLOATING; Data bus inputs are
FLOATING
Normal
TBD
TBD
44
44
mA
ICC7*
Operating bank interleave read current;
All bank interleaving reads, IOUT = 0mA; BL = 4, CL = CL(ICC), AL = tRCD(ICC)-1*tCK(ICC); tCK =
tCK(ICC), tRC = tRC(ICC), tRRD = tRRD(ICC), tRCD = 1*tCK(ICC); CKE is HIGH, CS# is HIGH between
valid commands; Address bus inputs are STABLE during DESELECTs; Data bus inputs are
switching.
TBD
TBD
2200
2160
mA
* Value calculated as one module rank in thes operating condition, and all other module ranks in ICC2P (CKE LOW) mode.
** Value calculated reflects all module ranks in this operating condition
NOTES:
• ICC specifications were calculated using SAMSUNG components. Other manufactures DRAMs may have different values.




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